x86: Setup correct TSL/TR segment attributes on INIT

The TSL/LDT & TR/TSS segments didn't contain valid attributes. This
caused problems when transfering the state into KVM where invalid
state is a no-go. Fixup the attributes with values from AMD's
architecture programmer's manual.

diff --git a/src/arch/x86/faults.cc b/src/arch/x86/faults.cc
index aa859052efbb75f648912f3fd5cd24acba6696d1..0cbf2334ec7bb04d2ad63b7bffc15edd0b36a80d 100644 (file)
--- a/src/arch/x86/faults.cc
+++ b/src/arch/x86/faults.cc
@@ -245,15 +245,21 @@ namespace X86ISA
         tc->setMiscReg(MISCREG_IDTR_BASE, 0);
         tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff);
 
+        SegAttr tslAttr = 0;
+        tslAttr.present = 1;
+        tslAttr.type = 2; // LDT
         tc->setMiscReg(MISCREG_TSL, 0);
         tc->setMiscReg(MISCREG_TSL_BASE, 0);
         tc->setMiscReg(MISCREG_TSL_LIMIT, 0xffff);
-        tc->setMiscReg(MISCREG_TSL_ATTR, 0);
+        tc->setMiscReg(MISCREG_TSL_ATTR, tslAttr);
 
+        SegAttr trAttr = 0;
+        trAttr.present = 1;
+        trAttr.type = 3; // Busy 16-bit TSS
         tc->setMiscReg(MISCREG_TR, 0);
         tc->setMiscReg(MISCREG_TR_BASE, 0);
         tc->setMiscReg(MISCREG_TR_LIMIT, 0xffff);
-        tc->setMiscReg(MISCREG_TR_ATTR, 0);
+        tc->setMiscReg(MISCREG_TR_ATTR, trAttr);
 
         // This value should be the family/model/stepping of the processor.
         // (page 418). It should be consistent with the value from CPUID, but