projects
/
riscv-isa-sim.git
/ commitdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
| commitdiff |
tree
raw
|
patch
| inline |
side by side
(parent:
0d984ad
)
attempting to get rv32 mv working
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Wed, 7 Nov 2018 09:20:42 +0000
(09:20 +0000)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Wed, 7 Nov 2018 09:20:42 +0000
(09:20 +0000)
id_regs.py
patch
|
blob
|
history
diff --git
a/id_regs.py
b/id_regs.py
index 03e255dc9c570bef9ae3f471a88fd2d4e6a60243..a1fdf6773d826244a3ab9bf9d7f9b3ef66fd7fcf 100644
(file)
--- a/
id_regs.py
+++ b/
id_regs.py
@@
-95,12
+95,12
@@
def find_registers(fname, insn, twin_predication, immed_offset, is_branch):
src_flen = 128
dest_flen = 128
if split[1].startswith('w'):
-
src
_flen = 32
+
dest
_flen = 32
elif split[1].startswith('d'):
-
src
_flen = 64
+
dest
_flen = 64
elif split[1].startswith('q'):
-
src
_flen = 128
-
el
if "f128(" in f:
+
dest
_flen = 128
+ if "f128(" in f:
src_flen = 128
dest_flen = 128
elif "f64(" in f or insn == 'fsd':