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 Managing IO on an ASIC is nowhere near as simple as on an FPGA.
 An FPGA has built-in IO Pads, the wires terminate inside an
-existing silicon block which has been tested for you.
+existing silicon block which has been tested for you.  In an
+ASIC, a bi-directional IO Pad requires three wires (in, out,
+out-enable) to be routed right the way from the ASIC, all
+the way to the IO PAD, where only then does a wire bond connect
+it to a single pin.
 
 Designing an ASIC, there is no guarantee that the IO pad is
 working when manufactured. Worse, the peripheral could be