litedram: l2: Add a few comments about litedram behaviour

litedram ignores a couple of signals of his "pseudo-axi" port,
this adds a bit of documentation around it.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

diff --git a/litedram/extras/litedram-wrapper-l2.vhdl b/litedram/extras/litedram-wrapper-l2.vhdl
index 669a23c8c311e1e0327b690b83077c881f65c0a3..5823f199149e5350e0202405c8ebf15934b7b4c5 100644 (file)
--- a/litedram/extras/litedram-wrapper-l2.vhdl
+++ b/litedram/extras/litedram-wrapper-l2.vhdl
@@ -914,6 +914,12 @@ begin
             user_port0_wdata_data(WBL*(i+1)-1 downto WBL*i) <= stq_data;
         end loop;
 
+        -- Note: Current litedram ignores user_port0_wdata_valid. We
+        -- must make sure to always have the data available at the
+        -- output of the store queue when we send the write command.
+        --
+        -- Thankfully this is always the case with this design.
+        --
         user_port0_wdata_valid <= storeq_rd_valid;
         storeq_rd_ready        <= user_port0_wdata_ready;
 
@@ -957,6 +963,9 @@ begin
             user_port0_cmd_valid <= refill_cmd_valid;
             user_port0_cmd_we    <= '0';
         end if;
+
+        -- Note: litedram  ignores this signal and assumes we are
+        -- always ready to accept read data.
         user_port0_rdata_ready <= '1'; -- Always 1
     end process;