struct r600_surface *cb = (struct r600_surface*)ctx->framebuffer.state.cbufs[i];
unsigned reloc = r600_context_bo_reloc(&ctx->b, &ctx->b.rings.gfx,
(struct r600_resource*)cb->base.texture,
- RADEON_USAGE_READWRITE);
+ RADEON_USAGE_READWRITE,
+ RADEON_PRIO_SHADER_RESOURCE_RW);
r600_write_compute_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 7);
radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
radeon_emit(cs, PKT3C(PKT3_NOP, 0, 0));
radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx,
- kernel->code_bo, RADEON_USAGE_READ));
+ kernel->code_bo, RADEON_USAGE_READ,
+ RADEON_PRIO_SHADER_DATA));
}
static void evergreen_launch_grid(
for (i = 0; i < ncopy; i++) {
csize = size < 0x000fffff ? size : 0x000fffff;
/* emit reloc before writting cs so that cs is always in consistent state */
- r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, rsrc, RADEON_USAGE_READ);
- r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, rdst, RADEON_USAGE_WRITE);
+ r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, rsrc, RADEON_USAGE_READ,
+ RADEON_PRIO_MIN);
+ r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, rdst, RADEON_USAGE_WRITE,
+ RADEON_PRIO_MIN);
cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_COPY, sub_cmd, csize);
cs->buf[cs->cdw++] = dst_offset & 0xffffffff;
cs->buf[cs->cdw++] = src_offset & 0xffffffff;
/* This must be done after r600_need_cs_space. */
reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx,
- (struct r600_resource*)dst, RADEON_USAGE_WRITE);
+ (struct r600_resource*)dst, RADEON_USAGE_WRITE,
+ RADEON_PRIO_MIN);
radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0));
radeon_emit(cs, clear_value); /* DATA [31:0] */
reloc = r600_context_bo_reloc(&rctx->b,
&rctx->b.rings.gfx,
(struct r600_resource*)cb->base.texture,
- RADEON_USAGE_READWRITE);
+ RADEON_USAGE_READWRITE,
+ tex->surface.nsamples > 1 ?
+ RADEON_PRIO_COLOR_BUFFER_MSAA :
+ RADEON_PRIO_COLOR_BUFFER);
if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
cmask_reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx,
- tex->cmask_buffer, RADEON_USAGE_READWRITE);
+ tex->cmask_buffer, RADEON_USAGE_READWRITE,
+ RADEON_PRIO_COLOR_META);
} else {
cmask_reloc = reloc;
}
unsigned reloc = r600_context_bo_reloc(&rctx->b,
&rctx->b.rings.gfx,
(struct r600_resource*)state->cbufs[0]->texture,
- RADEON_USAGE_READWRITE);
+ RADEON_USAGE_READWRITE,
+ RADEON_PRIO_COLOR_BUFFER);
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C70_CB_COLOR0_INFO */
radeon_emit(cs, reloc);
unsigned reloc = r600_context_bo_reloc(&rctx->b,
&rctx->b.rings.gfx,
(struct r600_resource*)state->zsbuf->texture,
- RADEON_USAGE_READWRITE);
+ RADEON_USAGE_READWRITE,
+ zb->base.texture->nr_samples > 1 ?
+ RADEON_PRIO_DEPTH_BUFFER_MSAA :
+ RADEON_PRIO_DEPTH_BUFFER);
r600_write_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
zb->pa_su_poly_offset_db_fmt_cntl);
r600_write_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
r600_write_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, a->rsurf->db_preload_control);
r600_write_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
- reloc_idx = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rtex->htile_buffer, RADEON_USAGE_READWRITE);
+ reloc_idx = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rtex->htile_buffer,
+ RADEON_USAGE_READWRITE, RADEON_PRIO_DEPTH_META);
cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
cs->buf[cs->cdw++] = reloc_idx;
} else {
radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD7 */
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
- radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer, RADEON_USAGE_READ));
+ radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
+ RADEON_USAGE_READ, RADEON_PRIO_SHADER_BUFFER_RO));
}
state->dirty_mask = 0;
}
}
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
- radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer, RADEON_USAGE_READ));
+ radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
+ RADEON_USAGE_READ, RADEON_PRIO_SHADER_BUFFER_RO));
radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
radeon_emit(cs, (buffer_id_base + buffer_index) * 8);
S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER));
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
- radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer, RADEON_USAGE_READ));
+ radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
+ RADEON_USAGE_READ, RADEON_PRIO_SHADER_BUFFER_RO));
dirty_mask &= ~(1 << buffer_index);
}
radeon_emit_array(cs, rview->tex_resource_words, 8);
reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rview->tex_resource,
- RADEON_USAGE_READ);
+ RADEON_USAGE_READ,
+ rview->tex_resource->b.b.nr_samples > 1 ?
+ RADEON_PRIO_SHADER_TEXTURE_MSAA :
+ RADEON_PRIO_SHADER_TEXTURE_RO);
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
radeon_emit(cs, reloc);
r600_write_context_reg(cs, R_0288A4_SQ_PGM_START_FS,
(r600_resource_va(rctx->b.b.screen, &shader->buffer->b.b) + shader->offset) >> 8);
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
- radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, shader->buffer, RADEON_USAGE_READ));
+ radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, shader->buffer,
+ RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA));
}
static void evergreen_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a)
r600_write_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE,
(r600_resource_va(screen, &rbuffer->b.b)) >> 8);
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
- radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer, RADEON_USAGE_READWRITE));
+ radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
+ RADEON_USAGE_READWRITE,
+ RADEON_PRIO_SHADER_RESOURCE_RW));
r600_write_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
state->esgs_ring.buffer_size >> 8);
r600_write_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE,
(r600_resource_va(screen, &rbuffer->b.b)) >> 8);
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
- radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer, RADEON_USAGE_READWRITE));
+ radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
+ RADEON_USAGE_READWRITE,
+ RADEON_PRIO_SHADER_RESOURCE_RW));
r600_write_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
state->gsvs_ring.buffer_size >> 8);
} else {
}
size = (cheight * pitch) >> 2;
/* emit reloc before writting cs so that cs is always in consistent state */
- r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, &rsrc->resource, RADEON_USAGE_READ);
- r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, &rdst->resource, RADEON_USAGE_WRITE);
+ r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, &rsrc->resource,
+ RADEON_USAGE_READ, RADEON_PRIO_MIN);
+ r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, &rdst->resource,
+ RADEON_USAGE_WRITE, RADEON_PRIO_MIN);
cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_COPY, sub_cmd, size);
cs->buf[cs->cdw++] = base >> 8;
cs->buf[cs->cdw++] = (detile << 31) | (array_mode << 27) |
}
/* This must be done after r600_need_cs_space. */
- src_reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, (struct r600_resource*)src, RADEON_USAGE_READ);
- dst_reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, (struct r600_resource*)dst, RADEON_USAGE_WRITE);
+ src_reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, (struct r600_resource*)src,
+ RADEON_USAGE_READ, RADEON_PRIO_MIN);
+ dst_reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, (struct r600_resource*)dst,
+ RADEON_USAGE_WRITE, RADEON_PRIO_MIN);
radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0));
radeon_emit(cs, src_offset); /* SRC_ADDR_LO [31:0] */
for (i = 0; i < ncopy; i++) {
csize = size < 0xffff ? size : 0xffff;
/* emit reloc before writting cs so that cs is always in consistent state */
- r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, rsrc, RADEON_USAGE_READ);
- r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, rdst, RADEON_USAGE_WRITE);
+ r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, rsrc, RADEON_USAGE_READ,
+ RADEON_PRIO_MIN);
+ r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, rdst, RADEON_USAGE_WRITE,
+ RADEON_PRIO_MIN);
cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_COPY, 0, 0, csize);
cs->buf[cs->cdw++] = dst_offset & 0xfffffffc;
cs->buf[cs->cdw++] = src_offset & 0xfffffffc;
reloc = r600_context_bo_reloc(&rctx->b,
&rctx->b.rings.gfx,
(struct r600_resource*)cb[i]->base.texture,
- RADEON_USAGE_READWRITE);
+ RADEON_USAGE_READWRITE,
+ cb[i]->base.texture->nr_samples > 1 ?
+ RADEON_PRIO_COLOR_BUFFER_MSAA :
+ RADEON_PRIO_COLOR_BUFFER);
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
radeon_emit(cs, reloc);
reloc = r600_context_bo_reloc(&rctx->b,
&rctx->b.rings.gfx,
cb[i]->cb_buffer_fmask,
- RADEON_USAGE_READWRITE);
+ RADEON_USAGE_READWRITE,
+ cb[i]->base.texture->nr_samples > 1 ?
+ RADEON_PRIO_COLOR_BUFFER_MSAA :
+ RADEON_PRIO_COLOR_BUFFER);
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
radeon_emit(cs, reloc);
reloc = r600_context_bo_reloc(&rctx->b,
&rctx->b.rings.gfx,
cb[i]->cb_buffer_cmask,
- RADEON_USAGE_READWRITE);
+ RADEON_USAGE_READWRITE,
+ cb[i]->base.texture->nr_samples > 1 ?
+ RADEON_PRIO_COLOR_BUFFER_MSAA :
+ RADEON_PRIO_COLOR_BUFFER);
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
radeon_emit(cs, reloc);
}
unsigned reloc = r600_context_bo_reloc(&rctx->b,
&rctx->b.rings.gfx,
(struct r600_resource*)state->zsbuf->texture,
- RADEON_USAGE_READWRITE);
+ RADEON_USAGE_READWRITE,
+ surf->base.texture->nr_samples > 1 ?
+ RADEON_PRIO_DEPTH_BUFFER_MSAA :
+ RADEON_PRIO_DEPTH_BUFFER);
r600_write_context_reg(cs, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
surf->pa_su_poly_offset_db_fmt_cntl);
r600_write_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
r600_write_context_reg(cs, R_028D24_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
r600_write_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
- reloc_idx = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rtex->htile_buffer, RADEON_USAGE_READWRITE);
+ reloc_idx = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rtex->htile_buffer,
+ RADEON_USAGE_READWRITE, RADEON_PRIO_DEPTH_META);
cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
cs->buf[cs->cdw++] = reloc_idx;
} else {
radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
- radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer, RADEON_USAGE_READ));
+ radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
+ RADEON_USAGE_READ, RADEON_PRIO_SHADER_BUFFER_RO));
}
}
}
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
- radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer, RADEON_USAGE_READ));
+ radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
+ RADEON_USAGE_READ, RADEON_PRIO_SHADER_BUFFER_RO));
radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
radeon_emit(cs, (buffer_id_base + buffer_index) * 7);
radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
- radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer, RADEON_USAGE_READ));
+ radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
+ RADEON_USAGE_READ, RADEON_PRIO_SHADER_BUFFER_RO));
dirty_mask &= ~(1 << buffer_index);
}
radeon_emit_array(cs, rview->tex_resource_words, 7);
reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rview->tex_resource,
- RADEON_USAGE_READ);
+ RADEON_USAGE_READ,
+ rview->tex_resource->b.b.nr_samples > 1 ?
+ RADEON_PRIO_SHADER_TEXTURE_MSAA :
+ RADEON_PRIO_SHADER_TEXTURE_RO);
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
radeon_emit(cs, reloc);
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
r600_write_context_reg(cs, R_028894_SQ_PGM_START_FS, shader->offset >> 8);
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
- radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, shader->buffer, RADEON_USAGE_READ));
+ radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, shader->buffer,
+ RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA));
}
static void r600_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a)
r600_write_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE,
(r600_resource_va(screen, &rbuffer->b.b)) >> 8);
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
- radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer, RADEON_USAGE_READWRITE));
+ radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
+ RADEON_USAGE_READWRITE,
+ RADEON_PRIO_SHADER_RESOURCE_RW));
r600_write_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
state->esgs_ring.buffer_size >> 8);
r600_write_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE,
(r600_resource_va(screen, &rbuffer->b.b)) >> 8);
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
- radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer, RADEON_USAGE_READWRITE));
+ radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
+ RADEON_USAGE_READWRITE,
+ RADEON_PRIO_SHADER_RESOURCE_RW));
r600_write_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
state->gsvs_ring.buffer_size >> 8);
} else {
cheight = cheight > copy_height ? copy_height : cheight;
size = (cheight * pitch) >> 2;
/* emit reloc before writting cs so that cs is always in consistent state */
- r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, &rsrc->resource, RADEON_USAGE_READ);
- r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, &rdst->resource, RADEON_USAGE_WRITE);
+ r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, &rsrc->resource, RADEON_USAGE_READ,
+ RADEON_PRIO_MIN);
+ r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, &rdst->resource, RADEON_USAGE_WRITE,
+ RADEON_PRIO_MIN);
cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_COPY, 1, 0, size);
cs->buf[cs->cdw++] = base >> 8;
cs->buf[cs->cdw++] = (detile << 31) | (array_mode << 27) |
cs->buf[cs->cdw++] = info.count;
cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA;
cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, rctx->b.predicate_drawing);
- cs->buf[cs->cdw++] = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, (struct r600_resource*)ib.buffer, RADEON_USAGE_READ);
+ cs->buf[cs->cdw++] = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx,
+ (struct r600_resource*)ib.buffer,
+ RADEON_USAGE_READ, RADEON_PRIO_MIN);
}
} else {
if (info.count_from_stream_output) {
cs->buf[cs->cdw++] = 0; /* unused */
cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
- cs->buf[cs->cdw++] = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, t->buf_filled_size, RADEON_USAGE_READ);
+ cs->buf[cs->cdw++] = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx,
+ t->buf_filled_size, RADEON_USAGE_READ,
+ RADEON_PRIO_MIN);
}
cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, rctx->b.predicate_drawing);
r600_emit_command_buffer(cs, &shader->command_buffer);
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
- radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, shader->bo, RADEON_USAGE_READ));
+ radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, shader->bo,
+ RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA));
}
unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
uint32_t reloc;
va = r600_resource_va(&rscreen->b.b, (void*)rscreen->b.trace_bo);
- reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rscreen->b.trace_bo, RADEON_USAGE_READWRITE);
+ reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rscreen->b.trace_bo,
+ RADEON_USAGE_READWRITE, RADEON_PRIO_MIN);
radeon_emit(cs, PKT3(PKT3_MEM_WRITE, 3, 0));
radeon_emit(cs, va & 0xFFFFFFFFUL);
radeon_emit(cs, (va >> 32UL) & 0xFFUL);
static INLINE unsigned r600_context_bo_reloc(struct r600_common_context *rctx,
struct r600_ring *ring,
struct r600_resource *rbo,
- enum radeon_bo_usage usage)
+ enum radeon_bo_usage usage,
+ enum radeon_bo_priority priority)
{
assert(usage);
}
}
return rctx->ws->cs_add_reloc(ring->cs, rbo->cs_buf, usage,
- rbo->domains, RADEON_PRIO_MIN) * 4;
+ rbo->domains, priority) * 4;
}
static INLINE void r600_emit_reloc(struct r600_common_context *rctx,
struct r600_ring *ring, struct r600_resource *rbo,
- enum radeon_bo_usage usage)
+ enum radeon_bo_usage usage,
+ enum radeon_bo_priority priority)
{
struct radeon_winsys_cs *cs = ring->cs;
bool has_vm = ((struct r600_common_screen*)rctx->b.screen)->info.r600_virtual_address;
- unsigned reloc = r600_context_bo_reloc(rctx, ring, rbo, usage);
+ unsigned reloc = r600_context_bo_reloc(rctx, ring, rbo, usage, priority);
if (!has_vm) {
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
default:
assert(0);
}
- r600_emit_reloc(ctx, &ctx->rings.gfx, query->buffer.buf, RADEON_USAGE_WRITE);
+ r600_emit_reloc(ctx, &ctx->rings.gfx, query->buffer.buf, RADEON_USAGE_WRITE,
+ RADEON_PRIO_MIN);
if (!r600_is_timer_query(query->type)) {
ctx->num_cs_dw_nontimer_queries_suspend += query->num_cs_dw;
default:
assert(0);
}
- r600_emit_reloc(ctx, &ctx->rings.gfx, query->buffer.buf, RADEON_USAGE_WRITE);
+ r600_emit_reloc(ctx, &ctx->rings.gfx, query->buffer.buf, RADEON_USAGE_WRITE,
+ RADEON_PRIO_MIN);
query->buffer.results_end += query->result_size;
radeon_emit(cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
radeon_emit(cs, (va + results_base) & 0xFFFFFFFFUL);
radeon_emit(cs, op | (((va + results_base) >> 32UL) & 0xFF));
- r600_emit_reloc(ctx, &ctx->rings.gfx, qbuf->buf, RADEON_USAGE_READ);
+ r600_emit_reloc(ctx, &ctx->rings.gfx, qbuf->buf, RADEON_USAGE_READ,
+ RADEON_PRIO_MIN);
results_base += query->result_size;
/* set CONTINUE bit for all packets except the first */
radeon_emit(cs, va);
radeon_emit(cs, va >> 32);
- r600_emit_reloc(ctx, &ctx->rings.gfx, buffer, RADEON_USAGE_WRITE);
+ r600_emit_reloc(ctx, &ctx->rings.gfx, buffer, RADEON_USAGE_WRITE, RADEON_PRIO_MIN);
/* analyze results */
results = r600_buffer_map_sync_with_rings(ctx, buffer, PIPE_TRANSFER_READ);
radeon_emit(cs, va >> 8); /* BUFFER_BASE */
r600_emit_reloc(rctx, &rctx->rings.gfx, r600_resource(t[i]->b.buffer),
- RADEON_USAGE_WRITE);
+ RADEON_USAGE_WRITE, RADEON_PRIO_SHADER_RESOURCE_RW);
/* R7xx requires this packet after updating BUFFER_BASE.
* Without this, R7xx locks up. */
radeon_emit(cs, va >> 8);
r600_emit_reloc(rctx, &rctx->rings.gfx, r600_resource(t[i]->b.buffer),
- RADEON_USAGE_WRITE);
+ RADEON_USAGE_WRITE, RADEON_PRIO_SHADER_RESOURCE_RW);
}
}
radeon_emit(cs, va >> 32); /* src address hi */
r600_emit_reloc(rctx, &rctx->rings.gfx, t[i]->buf_filled_size,
- RADEON_USAGE_READ);
+ RADEON_USAGE_READ, RADEON_PRIO_MIN);
} else {
/* Start from the beginning. */
radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
radeon_emit(cs, 0); /* unused */
r600_emit_reloc(rctx, &rctx->rings.gfx, t[i]->buf_filled_size,
- RADEON_USAGE_WRITE);
+ RADEON_USAGE_WRITE, RADEON_PRIO_MIN);
}
if (rctx->chip_class >= EVERGREEN) {
(struct pipe_resource*)kernel_args_buffer);
kernel_args_va += kernel_args_offset;
- si_pm4_add_bo(pm4, kernel_args_buffer, RADEON_USAGE_READ);
+ si_pm4_add_bo(pm4, kernel_args_buffer, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0, kernel_args_va);
si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0 + 4, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) | S_008F04_STRIDE(0));
if (!buffer) {
continue;
}
- si_pm4_add_bo(pm4, buffer, RADEON_USAGE_READWRITE);
+ si_pm4_add_bo(pm4, buffer, RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RESOURCE_RW);
}
/* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
}
shader_va = r600_resource_va(ctx->screen, (void *)shader->bo);
- si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
+ si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
si_pm4_set_reg(pm4, R_00B830_COMPUTE_PGM_LO, (shader_va >> 8) & 0xffffffff);
si_pm4_set_reg(pm4, R_00B834_COMPUTE_PGM_HI, shader_va >> 40);
PIPE_USAGE_DEFAULT,
SI_NUM_CONTEXTS * desc->context_size);
- r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, desc->buffer, RADEON_USAGE_READWRITE);
+ r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, desc->buffer,
+ RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_DATA);
va = r600_resource_va(sctx->b.b.screen, &desc->buffer->b.b);
/* We don't check for CS space here, because this should be called
si_release_descriptors(&views->desc);
}
+static enum radeon_bo_priority si_get_resource_ro_priority(struct r600_resource *res)
+{
+ if (res->b.b.target == PIPE_BUFFER)
+ return RADEON_PRIO_SHADER_BUFFER_RO;
+
+ if (res->b.b.nr_samples > 1)
+ return RADEON_PRIO_SHADER_TEXTURE_MSAA;
+
+ return RADEON_PRIO_SHADER_TEXTURE_RO;
+}
+
static void si_sampler_views_begin_new_cs(struct si_context *sctx,
struct si_sampler_views *views)
{
struct si_pipe_sampler_view *rview =
(struct si_pipe_sampler_view*)views->views[i];
- r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, rview->resource, RADEON_USAGE_READ);
+ r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
+ rview->resource, RADEON_USAGE_READ,
+ si_get_resource_ro_priority(rview->resource));
}
- r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, views->desc.buffer, RADEON_USAGE_READWRITE);
+ r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, views->desc.buffer,
+ RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_DATA);
si_emit_shader_pointer(sctx, &views->desc);
}
struct si_pipe_sampler_view *rview =
(struct si_pipe_sampler_view*)view;
- r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, rview->resource, RADEON_USAGE_READ);
+ r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
+ rview->resource, RADEON_USAGE_READ,
+ si_get_resource_ro_priority(rview->resource));
pipe_sampler_view_reference(&views->views[slot], view);
views->desc_data[slot] = view_desc;
struct si_buffer_resources *buffers,
unsigned num_buffers, unsigned shader,
unsigned shader_userdata_index,
- enum radeon_bo_usage shader_usage)
+ enum radeon_bo_usage shader_usage,
+ enum radeon_bo_priority priority)
{
int i;
buffers->num_buffers = num_buffers;
buffers->shader_usage = shader_usage;
+ buffers->priority = priority;
buffers->buffers = CALLOC(num_buffers, sizeof(struct pipe_resource*));
buffers->desc_storage = CALLOC(num_buffers, sizeof(uint32_t) * 4);
r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
(struct r600_resource*)buffers->buffers[i],
- buffers->shader_usage);
+ buffers->shader_usage, buffers->priority);
}
r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
- buffers->desc.buffer, RADEON_USAGE_READWRITE);
+ buffers->desc.buffer, RADEON_USAGE_READWRITE,
+ RADEON_PRIO_SHADER_DATA);
si_emit_shader_pointer(sctx, &buffers->desc);
}
buffers->buffers[slot] = buffer;
r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
- (struct r600_resource*)buffer, buffers->shader_usage);
+ (struct r600_resource*)buffer,
+ buffers->shader_usage, buffers->priority);
buffers->desc.enabled_mask |= 1 << slot;
} else {
/* Clear the descriptor. */
pipe_resource_reference(&buffers->buffers[slot], input->buffer);
r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
(struct r600_resource*)input->buffer,
- buffers->shader_usage);
+ buffers->shader_usage, buffers->priority);
buffers->desc.enabled_mask |= 1 << slot;
} else {
/* Clear the descriptor. */
buffer);
r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
(struct r600_resource*)buffer,
- buffers->shader_usage);
+ buffers->shader_usage, buffers->priority);
buffers->desc.enabled_mask |= 1 << bufidx;
} else {
/* Clear the descriptor and unset the resource. */
old_va, buf);
r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
- rbuffer, buffers->shader_usage);
+ rbuffer, buffers->shader_usage,
+ buffers->priority);
buffers->desc.dirty_mask |= 1 << i;
found = true;
old_va, buf);
r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
- rbuffer, buffers->shader_usage);
+ rbuffer, buffers->shader_usage,
+ buffers->priority);
buffers->desc.dirty_mask |= 1 << i;
found = true;
old_va, buf);
r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
- rbuffer, RADEON_USAGE_READ);
+ rbuffer, RADEON_USAGE_READ,
+ RADEON_PRIO_SHADER_BUFFER_RO);
views->desc.dirty_mask |= 1 << i;
found = true;
/* This must be done after need_cs_space. */
r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
- (struct r600_resource*)dst, RADEON_USAGE_WRITE);
+ (struct r600_resource*)dst, RADEON_USAGE_WRITE,
+ RADEON_PRIO_MIN);
/* Flush the caches for the first copy only.
* Also wait for the previous CP DMA operations. */
}
/* This must be done after r600_need_cs_space. */
- r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, (struct r600_resource*)src, RADEON_USAGE_READ);
- r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, (struct r600_resource*)dst, RADEON_USAGE_WRITE);
+ r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, (struct r600_resource*)src,
+ RADEON_USAGE_READ, RADEON_PRIO_MIN);
+ r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, (struct r600_resource*)dst,
+ RADEON_USAGE_WRITE, RADEON_PRIO_MIN);
si_emit_cp_dma_copy_buffer(sctx, dst_offset, src_offset, byte_count, sync_flags);
for (i = 0; i < SI_NUM_SHADERS; i++) {
si_init_buffer_resources(sctx, &sctx->const_buffers[i],
NUM_CONST_BUFFERS, i, SI_SGPR_CONST,
- RADEON_USAGE_READ);
+ RADEON_USAGE_READ, RADEON_PRIO_SHADER_BUFFER_RO);
si_init_buffer_resources(sctx, &sctx->rw_buffers[i],
i == PIPE_SHADER_VERTEX ?
SI_RW_SO + 4 : SI_RW_SO,
i, SI_SGPR_RW_BUFFERS,
- RADEON_USAGE_READWRITE);
+ RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RESOURCE_RW);
si_init_sampler_views(sctx, &sctx->samplers[i].views, i);
void si_pm4_add_bo(struct si_pm4_state *state,
struct r600_resource *bo,
- enum radeon_bo_usage usage)
+ enum radeon_bo_usage usage,
+ enum radeon_bo_priority priority)
{
unsigned idx = state->nbo++;
assert(idx < SI_PM4_MAX_BO);
r600_resource_reference(&state->bo[idx], bo);
state->bo_usage[idx] = usage;
+ state->bo_priority[idx] = priority;
}
void si_pm4_sh_data_begin(struct si_pm4_state *state)
struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
for (int i = 0; i < state->nbo; ++i) {
r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, state->bo[i],
- state->bo_usage[i]);
+ state->bo_usage[i], state->bo_priority[i]);
}
memcpy(&cs->buf[cs->cdw], state->pm4, state->ndw * 4);
unsigned nbo;
struct r600_resource *bo[SI_PM4_MAX_BO];
enum radeon_bo_usage bo_usage[SI_PM4_MAX_BO];
+ enum radeon_bo_priority bo_priority[SI_PM4_MAX_BO];
/* relocs for shader data */
unsigned nrelocs;
void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val);
void si_pm4_add_bo(struct si_pm4_state *state,
struct r600_resource *bo,
- enum radeon_bo_usage usage);
+ enum radeon_bo_usage usage,
+ enum radeon_bo_priority priority);
void si_pm4_sh_data_begin(struct si_pm4_state *state);
void si_pm4_sh_data_add(struct si_pm4_state *state, uint32_t dw);
sctx->fb_compressed_cb_mask |= 1 << i;
}
- si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
+ si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE,
+ rtex->surface.nsamples > 1 ? RADEON_PRIO_COLOR_BUFFER_MSAA :
+ RADEON_PRIO_COLOR_BUFFER);
si_pm4_set_reg(pm4, R_028C60_CB_COLOR0_BASE + i * 0x3C, surf->cb_color_base);
si_pm4_set_reg(pm4, R_028C64_CB_COLOR0_PITCH + i * 0x3C, surf->cb_color_pitch);
si_pm4_set_reg(pm4, R_028C68_CB_COLOR0_SLICE + i * 0x3C, surf->cb_color_slice);
}
if (surf->db_htile_data_base) {
- si_pm4_add_bo(pm4, rtex->htile_buffer, RADEON_USAGE_READWRITE);
+ si_pm4_add_bo(pm4, rtex->htile_buffer, RADEON_USAGE_READWRITE,
+ RADEON_PRIO_DEPTH_META);
}
si_pm4_set_reg(pm4, R_028008_DB_DEPTH_VIEW, surf->db_depth_view);
si_pm4_set_reg(pm4, R_028014_DB_HTILE_DATA_BASE, surf->db_htile_data_base);
si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, surf->db_depth_info);
si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, surf->db_z_info);
si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, surf->db_stencil_info);
- si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
+ si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE,
+ rtex->surface.nsamples > 1 ? RADEON_PRIO_DEPTH_BUFFER_MSAA :
+ RADEON_PRIO_DEPTH_BUFFER);
si_pm4_set_reg(pm4, R_028048_DB_Z_READ_BASE, surf->db_depth_base);
si_pm4_set_reg(pm4, R_02804C_DB_STENCIL_READ_BASE, surf->db_stencil_base);
si_pm4_set_reg(pm4, R_028050_DB_Z_WRITE_BASE, surf->db_depth_base);
if (sctx->b.chip_class >= CIK)
si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, va_offset >> 40);
sctx->b.ws->buffer_unmap(sctx->border_color_table->cs_buf);
- si_pm4_add_bo(pm4, sctx->border_color_table, RADEON_USAGE_READ);
+ si_pm4_add_bo(pm4, sctx->border_color_table, RADEON_USAGE_READ,
+ RADEON_PRIO_SHADER_DATA);
}
memcpy(samplers->samplers, states, sizeof(void*) * count);
struct si_descriptors desc;
unsigned num_buffers;
enum radeon_bo_usage shader_usage; /* READ, WRITE, or READWRITE */
+ enum radeon_bo_priority priority;
struct pipe_resource **buffers; /* this has num_buffers elements */
uint32_t *desc_storage; /* this has num_buffers*4 elements */
uint32_t **desc_data; /* an array of pointers pointing to desc_storage */
return;
va = r600_resource_va(ctx->screen, (void *)shader->bo);
- si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
+ si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
vgpr_comp_cnt = shader->shader.uses_instanceid ? 3 : 0;
si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, gs_vert_itemsize);
va = r600_resource_va(ctx->screen, (void *)shader->bo);
- si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
+ si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
return;
va = r600_resource_va(ctx->screen, (void *)shader->bo);
- si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
+ si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
vgpr_comp_cnt = shader->shader.uses_instanceid ? 3 : 0;
si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader->cb_shader_mask);
va = r600_resource_va(ctx->screen, (void *)shader->bo);
- si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
+ si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
si_pm4_sh_data_add(pm4, sctx->vertex_elements->rsrc_word3[i]);
if (!bound[ve->vertex_buffer_index]) {
- si_pm4_add_bo(pm4, rbuffer, RADEON_USAGE_READ);
+ si_pm4_add_bo(pm4, rbuffer, RADEON_USAGE_READ,
+ RADEON_PRIO_SHADER_BUFFER_RO);
bound[ve->vertex_buffer_index] = true;
}
}
si_pm4_cmd_add(pm4, va >> 32UL); /* src address hi */
si_pm4_cmd_add(pm4, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
si_pm4_cmd_add(pm4, 0); /* unused */
- si_pm4_add_bo(pm4, t->buf_filled_size, RADEON_USAGE_READ);
+ si_pm4_add_bo(pm4, t->buf_filled_size, RADEON_USAGE_READ,
+ RADEON_PRIO_MIN);
si_pm4_cmd_end(pm4, true);
}
va = r600_resource_va(&sctx->screen->b.b, ib->buffer);
va += ib->offset;
- si_pm4_add_bo(pm4, (struct r600_resource *)ib->buffer, RADEON_USAGE_READ);
+ si_pm4_add_bo(pm4, (struct r600_resource *)ib->buffer, RADEON_USAGE_READ,
+ RADEON_PRIO_MIN);
si_cmd_draw_index_2(pm4, max_size, va, info->count,
V_0287F0_DI_SRC_SEL_DMA,
sctx->b.predicate_drawing);
projects / mesa.git / commitdiff