arch-arm: Reduce boilerplate when extracting SelfDebug from tc

Change-Id: I1746400617be64ac9c2f3194442734e178342909
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31354
Tested-by: kokoro <noreply+kokoro@google.com>

diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index 300c82c2fe3a5094f0670be3db65d213ca8b2844..07d4ea8948c069ffdc923a5751089ae465c8a616 100644 (file)
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -723,8 +723,7 @@ ArmFault::invoke64(ThreadContext *tc, const StaticInstPtr &inst)
 bool
 ArmFault::vectorCatch(ThreadContext *tc, const StaticInstPtr &inst)
 {
-    auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
-    SelfDebug * sd = isa->getSelfDebug();
+    SelfDebug *sd = ArmISA::ISA::getSelfDebug(tc);
     VectorCatch* vc = sd->getVectorCatch(tc);
     if (!vc->isVCMatch()) {
         Fault fault = sd->testVectorCatch(tc, 0x0, this);

diff --git a/src/arch/arm/insts/pseudo.cc b/src/arch/arm/insts/pseudo.cc
index 3fe2dfa1115b12f97e9debd7cc858b3574677832..bf1fecc37f57cb168c3dda570bd59d499088150a 100644 (file)
--- a/src/arch/arm/insts/pseudo.cc
+++ b/src/arch/arm/insts/pseudo.cc
@@ -201,8 +201,11 @@ DebugStep::execute(ExecContext *xc, Trace::InstRecord *traceData) const
     PCState pc_state(xc->pcState());
     pc_state.debugStep(false);
     xc->pcState(pc_state);
-    auto *isa = static_cast<ArmISA::ISA *>(xc->tcBase()->getIsaPtr());
-    bool ldx = isa->getSelfDebug()->getSstep()->getLdx();
+
+    SelfDebug *sd = ArmISA::ISA::getSelfDebug(xc->tcBase());
+
+    bool ldx = sd->getSstep()->getLdx();
+
     return std::make_shared<SoftwareStepFault>(machInst, ldx,
                                                pc_state.stepped());
 

diff --git a/src/arch/arm/insts/static_inst.cc b/src/arch/arm/insts/static_inst.cc
index 12586c7562d1019645ea926920e6d3fa76e6febc..228149115c9505a205796206ffbdc2e359258ee8 100644 (file)
--- a/src/arch/arm/insts/static_inst.cc
+++ b/src/arch/arm/insts/static_inst.cc
@@ -1192,8 +1192,8 @@ ArmStaticInst::getPSTATEFromPSR(ThreadContext *tc, CPSR cpsr, CPSR spsr) const
         new_cpsr.daif = spsr.daif;
     }
 
-    auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
-    SoftwareStep * ss = (isa->getSelfDebug())->getSstep();
+    SelfDebug *sd = ArmISA::ISA::getSelfDebug(tc);
+    SoftwareStep *ss = sd->getSstep();
     new_cpsr.ss = ss->debugExceptionReturnSS(tc, spsr, dest, new_cpsr.width);
 
     return new_cpsr;

diff --git a/src/arch/arm/insts/static_inst.hh b/src/arch/arm/insts/static_inst.hh
index 2677a105c90c9ab81a900774ed27e2c188ab750d..e101d93fa8fec078271ca9da5f4b7943032b8e7f 100644 (file)
--- a/src/arch/arm/insts/static_inst.hh
+++ b/src/arch/arm/insts/static_inst.hh
@@ -203,8 +203,7 @@ class ArmStaticInst : public StaticInst
     static void
     activateBreakpoint(ThreadContext *tc)
     {
-        auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
-        SelfDebug * sd = isa->getSelfDebug();
+        SelfDebug *sd = ArmISA::ISA::getSelfDebug(tc);
         sd->activateDebug();
     }
 

diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 3b90de1346949b0139ac93c4a933748ec630537c..1713da076bd45c01f9baf1f7b4ea2902470bf93a 100644 (file)
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -466,10 +466,19 @@ namespace ArmISA
         void initID64(const ArmISAParams *p);
 
       public:
-        SelfDebug * getSelfDebug()
+        SelfDebug*
+        getSelfDebug() const
         {
             return selfDebug;
         }
+
+        static SelfDebug*
+        getSelfDebug(ThreadContext *tc)
+        {
+            auto *arm_isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
+            return arm_isa->getSelfDebug();
+        }
+
         RegVal readMiscRegNoEffect(int misc_reg) const;
         RegVal readMiscReg(int misc_reg);
         void setMiscRegNoEffect(int misc_reg, RegVal val);

diff --git a/src/arch/arm/isa/insts/ldr.isa b/src/arch/arm/isa/insts/ldr.isa
index 37abb6456f5db4c1c5b4f7f896ecdfef06e3ff42..d7e27a481ff06159f500281ffbdbfd17543ded55 100644 (file)
--- a/src/arch/arm/isa/insts/ldr.isa
+++ b/src/arch/arm/isa/insts/ldr.isa
@@ -211,9 +211,8 @@ let {{
 
             if self.flavor in ('exclusive', 'acex'):
                 accCode += '''
-           auto *isa = static_cast<ArmISA::ISA *>(xc->tcBase()->getIsaPtr());
-           SelfDebug * sd = isa->getSelfDebug();
-           sd->getSstep()->setLdx();
+                SelfDebug *sd = ArmISA::ISA::getSelfDebug(xc->tcBase());
+                sd->getSstep()->setLdx();
               '''
 
             self.codeBlobs["memacc_code"] = accCode
@@ -293,9 +292,8 @@ let {{
                 '''
             if self.flavor in ('exclusive', 'acex'):
                 accCode += '''
-             auto *isa = static_cast<ArmISA::ISA *>(xc->tcBase()->getIsaPtr());
-             SelfDebug * sd = isa->getSelfDebug();
-             sd->getSstep()->setLdx();
+                SelfDebug *sd = ArmISA::ISA::getSelfDebug(xc->tcBase());
+                sd->getSstep()->setLdx();
              '''
 
             self.codeBlobs["memacc_code"] = accCode

diff --git a/src/arch/arm/isa/insts/ldr64.isa b/src/arch/arm/isa/insts/ldr64.isa
index c9db190173617c07771db271680a90d3db8bf931..2cbc8b640da1fb1ca71e711b6ae50d7e97b21965 100644 (file)
--- a/src/arch/arm/isa/insts/ldr64.isa
+++ b/src/arch/arm/isa/insts/ldr64.isa
@@ -243,9 +243,8 @@ let {{
             accCode = accCode % buildMemSuffix(self.sign, self.size)
             if self.flavor in ('exclusive', 'acex'):
                 accCode += '''
-             auto *isa = static_cast<ArmISA::ISA *>(xc->tcBase()->getIsaPtr());
-             SelfDebug * sd = isa->getSelfDebug();
-             sd->getSstep()->setLdx();
+                SelfDebug *sd = ArmISA::ISA::getSelfDebug(xc->tcBase());
+                sd->getSstep()->setLdx();
              '''
             self.codeBlobs["memacc_code"] = accCode
             if accEpilogCode:
@@ -344,9 +343,8 @@ let {{
                         '''
             if self.flavor in ('exp', 'acexp'):
                 accCode += '''
-             auto *isa = static_cast<ArmISA::ISA *>(xc->tcBase()->getIsaPtr());
-             SelfDebug * sd = isa->getSelfDebug();
-             sd->getSstep()->setLdx();
+                SelfDebug *sd = ArmISA::ISA::getSelfDebug(xc->tcBase());
+                sd->getSstep()->setLdx();
              '''
             self.codeBlobs["memacc_code"] = accCode
             if accEpilogCode:

diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index a6205ced3a30c189ac26f30daeed991d818cb9d6..f67475bf36fc468514882b255f6ccb763079db9a 100644 (file)
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -1234,8 +1234,7 @@ TLB::translateFs(const RequestPtr &req, ThreadContext *tc, Mode mode,
 
     //Check for Debug Exceptions
     if (fault == NoFault) {
-        auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
-        SelfDebug *sd = isa->getSelfDebug();
+        SelfDebug *sd = ArmISA::ISA::getSelfDebug(tc);
 
         fault = sd->testDebug(tc, req, mode);
     }