+1999-01-18 Vladimir N. Makarov <vmakarov@cygnus.com>
+
+ * invoke.texi (-mcpu=740, -mcpu=750): New options.
+ (-m(no-)multiple, -m(no-)string): Describe cases for PPC740 &
+ PPC750.
+
+1999-01-18 Michael Meissner <meissner@cygnus.com>
+
+ * rs6000.h ({ASM,CPP}_CPU_SPEC): Add support for all machines
+ supported with -mcpu=xxx.
+ (processor_type): Add PROCESSOR_PPC750.
+ (ADJUST_PRIORITY): Call rs6000_adjust_priority.
+ (RTX_COSTS): Supply costs for 750 multiply/divide operations.
+ (rs6000_adjust_priority): Add declaration.
+
+ * rs6000.c (rs6000_override_options): -mcpu={750,740} now sets the
+ processor type as 750, not 603. Allow -mmultiple and -mstring on
+ little endian 750 systems.
+ (rs6000_adjust_priority): Stub for now.
+ (get_issue_rate): The PowerPC 750 can issue 2 instructions/cycle.
+
+ * rs6000.md (function/cpu attributes): Add initial ppc750 support.
+
+ * sysv4.h (STRICT_ALIGNMENT): Don't force strict alignment if
+ little endian.
+ (CC1_SPEC): Pass -mstrict-align if little endian, and not
+ overridden.
+ (CC1_ENDIAN_{LITTLE,BIG,DEFAULT}_SPEC): Endian specific configs.
+ (SUBTARGET_EXTRA_SPECS): Add cc1 endian specs.
+
+ * {sysv4,eabi}le.h (CC1_ENDIAN_DEFAULT_SPEC): Override, default is
+ little endian.
+
+ * t-ppcgas (MULTILIB_*): Delete obsolete Solaris multilibs.
+
Mon Jan 18 12:03:08 1999 Gavin Romig-Koch <gavin@cygnus.com>
* config/mips/mips.md (div_trap): Split div_trap_mips16
#undef CPP_ENDIAN_DEFAULT_SPEC
#define CPP_ENDIAN_DEFAULT_SPEC "%(cpp_endian_little)"
+#undef CC1_ENDIAN_DEFAULT_SPEC
+#define CC1_ENDIAN_DEFAULT_SPEC "%(cc1_endian_little)"
+
#undef LINK_TARGET_SPEC
#define LINK_TARGET_SPEC "\
%{mbig: -oformat elf32-powerpc } %{mbig-endian: -oformat elf32-powerpc } \
{"620", PROCESSOR_PPC620,
MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
POWER_MASKS | MASK_PPC_GPOPT},
+ {"740", PROCESSOR_PPC750,
+ MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
+ POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
+ {"750", PROCESSOR_PPC750,
+ MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
+ POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
{"801", PROCESSOR_MPCCORE,
MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
if (TARGET_STRING_SET)
target_flags = (target_flags & ~MASK_STRING) | string;
- /* Don't allow -mmultiple or -mstring on little endian systems, because the
- hardware doesn't support the instructions used in little endian mode */
- if (!BYTES_BIG_ENDIAN)
+ /* Don't allow -mmultiple or -mstring on little endian systems unless the cpu
+ is a 750, because the hardware doesn't support the instructions used in
+ little endian mode, and causes an alignment trap. The 750 does not cause
+ an alignment trap (except when the target is unaligned). */
+
+ if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
{
if (TARGET_MULTIPLE)
{
return cost;
}
+/* A C statement (sans semicolon) to update the integer scheduling priority
+ INSN_PRIORITY (INSN). Reduce the priority to execute the INSN earlier,
+ increase the priority to execute INSN later. Do not define this macro if
+ you do not need to adjust the scheduling priorities of insns. */
+
+int
+rs6000_adjust_priority (insn, priority)
+ rtx insn;
+ int priority;
+{
+ /* On machines (like the 750) which have asymetric integer units, where one
+ integer unit can do multiply and divides and the other can't, reduce the
+ priority of multiply/divide so it is scheduled before other integer
+ operationss. */
+
+#if 0
+ if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
+ return priority;
+
+ if (GET_CODE (PATTERN (insn)) == USE)
+ return priority;
+
+ switch (rs6000_cpu_attr) {
+ case CPU_PPC750:
+ switch (get_attr_type (insn))
+ {
+ default:
+ break;
+
+ case TYPE_IMUL:
+ case TYPE_IDIV:
+ fprintf (stderr, "priority was %#x (%d) before adjustment\n", priority, priority);
+ if (priority >= 0 && priority < 0x01000000)
+ priority >>= 3;
+ break;
+ }
+ }
+#endif
+
+ return priority;
+}
+
/* Return how many instructions the machine can issue per cycle */
int get_issue_rate()
{
return 3; /* ? */
case CPU_PPC603:
return 2;
+ case CPU_PPC750:
+ return 2;
case CPU_PPC604:
return 4;
case CPU_PPC604E:
%{mcpu=604: -D_ARCH_PPC} \
%{mcpu=604e: -D_ARCH_PPC} \
%{mcpu=620: -D_ARCH_PPC} \
+%{mcpu=740: -D_ARCH_PPC} \
+%{mcpu=750: -D_ARCH_PPC} \
+%{mcpu=801: -D_ARCH_PPC} \
%{mcpu=821: -D_ARCH_PPC} \
%{mcpu=823: -D_ARCH_PPC} \
%{mcpu=860: -D_ARCH_PPC}"
%{mcpu=604: -mppc} \
%{mcpu=604e: -mppc} \
%{mcpu=620: -mppc} \
+%{mcpu=740: -mppc} \
+%{mcpu=750: -mppc} \
+%{mcpu=801: -mppc} \
%{mcpu=821: -mppc} \
%{mcpu=823: -mppc} \
%{mcpu=860: -mppc}"
/* Processor type. Order must match cpu attribute in MD file. */
enum processor_type
- {PROCESSOR_RIOS1,
- PROCESSOR_RIOS2,
- PROCESSOR_MPCCORE,
- PROCESSOR_PPC403,
- PROCESSOR_PPC601,
- PROCESSOR_PPC603,
- PROCESSOR_PPC604,
- PROCESSOR_PPC604e,
- PROCESSOR_PPC620};
+ {
+ PROCESSOR_RIOS1,
+ PROCESSOR_RIOS2,
+ PROCESSOR_MPCCORE,
+ PROCESSOR_PPC403,
+ PROCESSOR_PPC601,
+ PROCESSOR_PPC603,
+ PROCESSOR_PPC604,
+ PROCESSOR_PPC604e,
+ PROCESSOR_PPC620,
+ PROCESSOR_PPC750
+};
extern enum processor_type rs6000_cpu;
#define ADJUST_COST(INSN,LINK,DEP_INSN,COST) \
(COST) = rs6000_adjust_cost (INSN,LINK,DEP_INSN,COST)
+/* A C statement (sans semicolon) to update the integer scheduling priority
+ INSN_PRIORITY (INSN). Reduce the priority to execute the INSN earlier,
+ increase the priority to execute INSN later. Do not define this macro if
+ you do not need to adjust the scheduling priorities of insns. */
+
+#define ADJUST_PRIORITY(INSN) \
+ INSN_PRIORITY (INSN) = rs6000_adjust_priority (INSN, INSN_PRIORITY (INSN))
+
/* Define this macro to change register usage conditional on target flags.
Set MQ register fixed (already call_used) if not POWER architecture
(RIOS1, RIOS2, RSC, and PPC601) so that it will not be allocated.
case PROCESSOR_PPC601: \
return COSTS_N_INSNS (5); \
case PROCESSOR_PPC603: \
+ case PROCESSOR_PPC750: \
return (GET_CODE (XEXP (X, 1)) != CONST_INT \
? COSTS_N_INSNS (5) \
: INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \
case PROCESSOR_PPC604e: \
case PROCESSOR_PPC620: \
return COSTS_N_INSNS (20); \
+ case PROCESSOR_PPC750: \
+ return COSTS_N_INSNS (19); \
} \
case FFS: \
return COSTS_N_INSNS (4); \
extern void rs6000_gen_section_name ();
extern void output_function_profiler ();
extern int rs6000_adjust_cost ();
+extern int rs6000_adjust_priority ();
extern void rs6000_trampoline_template ();
extern int rs6000_trampoline_size ();
extern void rs6000_initialize_trampoline ();
;; Processor type -- this attribute must exactly match the processor_type
;; enumeration in rs6000.h.
-(define_attr "cpu" "rios1,rios2,mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620"
+(define_attr "cpu" "rios1,rios2,mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc750"
(const (symbol_ref "rs6000_cpu_attr")))
; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
; (POWER and 601 use Integer Unit)
(define_function_unit "lsu" 1 0
(and (eq_attr "type" "load")
- (eq_attr "cpu" "mpccore,ppc603,ppc604,ppc604e,ppc620"))
+ (eq_attr "cpu" "mpccore,ppc603,ppc604,ppc604e,ppc620,ppc750"))
2 1)
(define_function_unit "lsu" 1 0
(and (eq_attr "type" "store,fpstore")
- (eq_attr "cpu" "mpccore,ppc603,ppc604,ppc604e,ppc620"))
+ (eq_attr "cpu" "mpccore,ppc603,ppc604,ppc604e,ppc620,ppc750"))
1 1)
(define_function_unit "lsu" 1 0
(and (eq_attr "type" "fpload")
- (eq_attr "cpu" "mpccore,ppc603"))
+ (eq_attr "cpu" "mpccore,ppc603,ppc750"))
2 1)
(define_function_unit "lsu" 1 0
(eq_attr "cpu" "ppc604,ppc604e,ppc620"))
20 19)
+; PPC750 has two integer units: a primary one which can perform all
+; operations and a secondary one which is fed in lock step with the first
+; and can perform "simple" integer operations.
+; To catch this we define a 'dummy' imuldiv-unit that is also needed
+; for the complex insns.
+(define_function_unit "iu2" 2 0
+ (and (eq_attr "type" "integer")
+ (eq_attr "cpu" "ppc750"))
+ 1 1)
+
+(define_function_unit "iu2" 2 0
+ (and (eq_attr "type" "imul")
+ (eq_attr "cpu" "ppc750"))
+ 4 2)
+
+(define_function_unit "imuldiv" 1 0
+ (and (eq_attr "type" "imul")
+ (eq_attr "cpu" "ppc750"))
+ 4 2)
+
+(define_function_unit "imuldiv" 1 0
+ (and (eq_attr "type" "idiv")
+ (eq_attr "cpu" "ppc750"))
+ 19 19)
+
; compare is done on integer unit, but feeds insns which
; execute on the branch unit.
(define_function_unit "iu" 1 0
(define_function_unit "iu" 1 0
(and (eq_attr "type" "compare,delayed_compare")
- (eq_attr "cpu" "mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620"))
+ (eq_attr "cpu" "mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc750"))
3 1)
(define_function_unit "iu2" 2 0
(define_function_unit "iu2" 2 0
(and (eq_attr "type" "compare,delayed_compare")
- (eq_attr "cpu" "ppc604,ppc604e,ppc620"))
+ (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc750"))
1 1)
; fp compare uses fp unit
; fp compare uses fp unit
(define_function_unit "fpu" 1 0
(and (eq_attr "type" "fpcompare")
- (eq_attr "cpu" "ppc601,ppc603,ppc604,ppc604e,ppc620"))
+ (eq_attr "cpu" "ppc601,ppc603,ppc604,ppc604e,ppc620,ppc750"))
5 1)
(define_function_unit "fpu" 1 0
(define_function_unit "bpu" 1 0
(and (eq_attr "type" "mtjmpr")
- (eq_attr "cpu" "mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620"))
+ (eq_attr "cpu" "mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc750"))
4 1)
; all jumps/branches are executing on the bpu, in 1 cycle, for all machines.
(define_function_unit "fpu" 1 0
(and (eq_attr "type" "fp")
- (eq_attr "cpu" "ppc603,ppc604,ppc604e,ppc620"))
+ (eq_attr "cpu" "ppc603,ppc604,ppc604e,ppc620,ppc750"))
3 1)
(define_function_unit "fpu" 1 0
; is this true?
(define_function_unit "fpu" 1 0
(and (eq_attr "type" "dmul")
- (eq_attr "cpu" "ppc603"))
+ (eq_attr "cpu" "ppc603,ppc750"))
4 2)
(define_function_unit "fpu" 1 0
(define_function_unit "fpu" 1 0
(and (eq_attr "type" "ddiv")
- (eq_attr "cpu" "ppc601,ppc604,ppc604e,ppc620"))
+ (eq_attr "cpu" "ppc601,ppc604,ppc604e,ppc620,ppc750"))
31 31)
(define_function_unit "fpu" 1 0
/* Define this macro to be the value 1 if instructions will fail to
work if given data not on the nominal alignment. If instructions
- will merely go slower in that case, define this macro as 0.
-
- Note, little endian systems trap on unaligned addresses, so never
- turn off strict alignment in that case. */
+ will merely go slower in that case, define this macro as 0. */
#undef STRICT_ALIGNMENT
-#define STRICT_ALIGNMENT (TARGET_STRICT_ALIGN || TARGET_LITTLE_ENDIAN)
+#define STRICT_ALIGNMENT (TARGET_STRICT_ALIGN)
/* Alignment in bits of the stack boundary. Note, in order to allow building
one set of libraries with -mno-eabi instead of eabi libraries and non-eabi
%{memb} %{!memb: %{msdata: -memb} %{msdata=eabi: -memb}} \
%{mlittle} %{mlittle-endian} %{mbig} %{mbig-endian} \
%{!mlittle: %{!mlittle-endian: %{!mbig: %{!mbig-endian: \
- %{mcall-solaris: -mlittle -msolaris} %{mcall-linux: -mbig} }}}}"
+ %{mcall-solaris: -mlittle -msolaris} \
+ %{mcall-linux: -mbig} }}}}"
+
+#ifndef CC1_ENDIAN_BIG_SPEC
+#define CC1_ENDIAN_BIG_SPEC ""
+#endif
+
+#ifndef CC1_ENDIAN_LITTLE_SPEC
+#define CC1_ENDIAN_LITTLE_SPEC "\
+%{!mstrict-align: %{!mno-strict-align: \
+ -mstrict-align \
+}}"
+#endif
+
+#ifndef CC1_ENDIAN_DEFAULT_SPEC
+#define CC1_ENDIAN_DEFAULT_SPEC "%(cc1_endian_big_spec)"
+#endif
#undef CC1_SPEC
/* Pass -G xxx to the compiler and set correct endian mode */
#define CC1_SPEC "%{G*} \
-%{!mlittle: %{!mlittle-endian: %{!mbig: %{!mbig-endian: \
- %{mcall-nt: -mlittle } \
- %{mcall-aixdesc: -mbig } \
- %{mcall-solaris: -mlittle } \
- %{mcall-linux: -mbig} }}}} \
+%{mlittle: %(cc1_endian_little)} %{!mlittle: %{mlittle-endian: %(cc1_endian_little)}} \
+%{mbig: %(cc1_endian_big)} %{!mbig: %{mbig-endian: %(cc1_endian_big)}} \
+ %{mcall-nt: -mlittle %{cc1_endian_little} } \
+ %{mcall-aixdesc: -mbig %{cc1_endian_big} } \
+ %{mcall-solaris: -mlittle %{cc1_endian_little} } \
+ %{mcall-linux: -mbig %{cc1_endian_big}}} \
+ %{!mcall-nt: %{!mcall-aixdesc: %{!mcall-solaris: %{!mcall-linux: \
+ %(cc1_endian_default) \
+ }}}} \
+}}} \
%{mcall-solaris: -mregnames } \
%{mno-sdata: -msdata=none } \
%{meabi: %{!mcall-*: -mcall-sysv }} \
{ "link_os_linux", LINK_OS_LINUX_SPEC }, \
{ "link_os_solaris", LINK_OS_SOLARIS_SPEC }, \
{ "link_os_default", LINK_OS_DEFAULT_SPEC }, \
+ { "cc1_endian_big", CC1_ENDIAN_BIG_SPEC }, \
+ { "cc1_endian_little", CC1_ENDIAN_LITTLE_SPEC }, \
+ { "cc1_endian_default", CC1_ENDIAN_DEFAULT_SPEC }, \
{ "cpp_endian_big", CPP_ENDIAN_BIG_SPEC }, \
{ "cpp_endian_little", CPP_ENDIAN_LITTLE_SPEC }, \
{ "cpp_endian_solaris", CPP_ENDIAN_SOLARIS_SPEC }, \
#undef CPP_ENDIAN_DEFAULT_SPEC
#define CPP_ENDIAN_DEFAULT_SPEC "%(cpp_endian_little)"
+#undef CC1_ENDIAN_DEFAULT_SPEC
+#define CC1_ENDIAN_DEFAULT_SPEC "%(cc1_endian_little)"
+
#undef LINK_TARGET_SPEC
#define LINK_TARGET_SPEC "\
%{mbig: -oformat elf32-powerpc } %{mbig-endian: -oformat elf32-powerpc } \
MULTILIB_OPTIONS = msoft-float \
mlittle/mbig \
- mcall-sysv/mcall-aix/mcall-solaris/mcall-linux
+ mcall-sysv/mcall-aix/mcall-linux
MULTILIB_DIRNAMES = nof \
le be \
- cs ca sol lin
+ cs ca lin
MULTILIB_EXTRA_OPTS = mrelocatable-lib mno-eabi mstrict-align
-MULTILIB_EXCEPTIONS = *mbig/*mcall-solaris* \
- *mlittle/*mcall-solaris* \
- *msoft-float/*mcall-solaris* \
- *mbig/*mcall-linux* \
+MULTILIB_EXCEPTIONS = *mbig/*mcall-linux* \
*mlittle/*mcall-linux* \
*msoft-float/*mcall-linux*
instruction scheduling parameters for machine type @var{cpu_type}.
Supported values for @var{cpu_type} are @samp{rs6000}, @samp{rios1},
@samp{rios2}, @samp{rsc}, @samp{601}, @samp{602}, @samp{603},
-@samp{603e}, @samp{604}, @samp{604e}, @samp{620}, @samp{power},
-@samp{power2}, @samp{powerpc}, @samp{403}, @samp{505}, @samp{801},
-@samp{821}, @samp{823}, and @samp{860} and @samp{common}.
-@samp{-mcpu=power}, @samp{-mcpu=power2}, and @samp{-mcpu=powerpc}
-specify generic POWER, POWER2 and pure PowerPC (i.e., not MPC601)
-architecture machine types, with an appropriate, generic processor model
-assumed for scheduling purposes.@refill
+@samp{603e}, @samp{604}, @samp{604e}, @samp{620}, @samp{740},
+@samp{750}, @samp{power}, @samp{power2}, @samp{powerpc}, @samp{403},
+@samp{505}, @samp{801}, @samp{821}, @samp{823}, and @samp{860} and
+@samp{common}. @samp{-mcpu=power}, @samp{-mcpu=power2}, and
+@samp{-mcpu=powerpc} specify generic POWER, POWER2 and pure PowerPC
+(i.e., not MPC601) architecture machine types, with an appropriate,
+generic processor model assumed for scheduling purposes.@refill
@c overfull hbox here --bob 22 jul96
@c original text between ignore ... end ignore
instructions are generated by default on POWER systems, and not
generated on PowerPC systems. Do not use @samp{-mmultiple} on little
endian PowerPC systems, since those instructions do not work when the
-processor is in little endian mode.
+processor is in little endian mode. The exceptions are PPC740 and
+PPC750 which permit the instructions usage in little endian mode.
@item -mstring
@itemx -mno-string
@kindex -mstring
-Generate code that uses (does not use) the load string instructions and the
-store string word instructions to save multiple registers and do small block
-moves. These instructions are generated by default on POWER systems, and not
-generated on PowerPC systems. Do not use @samp{-mstring} on little endian
-PowerPC systems, since those instructions do not work when the processor is in
-little endian mode.
+Generate code that uses (does not use) the load string instructions
+and the store string word instructions to save multiple registers and
+do small block moves. These instructions are generated by default on
+POWER systems, and not generated on PowerPC systems. Do not use
+@samp{-mstring} on little endian PowerPC systems, since those
+instructions do not work when the processor is in little endian mode.
+The exceptions are PPC740 and PPC750 which permit the instructions
+usage in little endian mode.
@item -mupdate
@itemx -mno-update
projects / gcc.git / commitdiff