verilog: fix unary operator conversion

diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index 979005b170e534c6db8cb7b79ee49c5464ecc96b..05b231cc5e24546710fa282c2e05ecc81418d5d8 100644 (file)
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -23,7 +23,7 @@ def _printexpr(ns, node):
        elif isinstance(node, Operator):
                arity = len(node.operands)
                if arity == 1:
-                       r = self.op + _printexpr(ns, node.operands[0])
+                       r = node.op + _printexpr(ns, node.operands[0])
                elif arity == 2:
                        r = _printexpr(ns, node.operands[0]) + " " + node.op + " " + _printexpr(ns, node.operands[1])
                else: