[ARM][GCC][5/5x]: MVE ACLE load intrinsics which load a byte, halfword, or word from...

author Srinath Parvathaneni <srinath.parvathaneni@arm.com>

Wed, 18 Mar 2020 18:48:05 +0000 (18:48 +0000)

committer Kyrylo Tkachov <kyrylo.tkachov@arm.com>

Wed, 18 Mar 2020 18:48:05 +0000 (18:48 +0000)
author Srinath Parvathaneni <srinath.parvathaneni@arm.com>
Wed, 18 Mar 2020 18:48:05 +0000 (18:48 +0000)
committer Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Wed, 18 Mar 2020 18:48:05 +0000 (18:48 +0000)
diff --git a/gcc/ChangeLog b/gcc/ChangeLog

index 4d4f9b1ec639267494fa6f3bc3eaadde46299df3..657683d21cde467b23613275e7f38b0b1b4cab4b 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,122 @@
+2020-03-18  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+            Mihail Ionescu  <mihail.ionescu@arm.com>
+            Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
+
+       * config/arm/arm_mve.h (vld1q_s8): Define macro.
+       (vld1q_s32): Likewise.
+       (vld1q_s16): Likewise.
+       (vld1q_u8): Likewise.
+       (vld1q_u32): Likewise.
+       (vld1q_u16): Likewise.
+       (vldrhq_gather_offset_s32): Likewise.
+       (vldrhq_gather_offset_s16): Likewise.
+       (vldrhq_gather_offset_u32): Likewise.
+       (vldrhq_gather_offset_u16): Likewise.
+       (vldrhq_gather_offset_z_s32): Likewise.
+       (vldrhq_gather_offset_z_s16): Likewise.
+       (vldrhq_gather_offset_z_u32): Likewise.
+       (vldrhq_gather_offset_z_u16): Likewise.
+       (vldrhq_gather_shifted_offset_s32): Likewise.
+       (vldrhq_gather_shifted_offset_s16): Likewise.
+       (vldrhq_gather_shifted_offset_u32): Likewise.
+       (vldrhq_gather_shifted_offset_u16): Likewise.
+       (vldrhq_gather_shifted_offset_z_s32): Likewise.
+       (vldrhq_gather_shifted_offset_z_s16): Likewise.
+       (vldrhq_gather_shifted_offset_z_u32): Likewise.
+       (vldrhq_gather_shifted_offset_z_u16): Likewise.
+       (vldrhq_s32): Likewise.
+       (vldrhq_s16): Likewise.
+       (vldrhq_u32): Likewise.
+       (vldrhq_u16): Likewise.
+       (vldrhq_z_s32): Likewise.
+       (vldrhq_z_s16): Likewise.
+       (vldrhq_z_u32): Likewise.
+       (vldrhq_z_u16): Likewise.
+       (vldrwq_s32): Likewise.
+       (vldrwq_u32): Likewise.
+       (vldrwq_z_s32): Likewise.
+       (vldrwq_z_u32): Likewise.
+       (vld1q_f32): Likewise.
+       (vld1q_f16): Likewise.
+       (vldrhq_f16): Likewise.
+       (vldrhq_z_f16): Likewise.
+       (vldrwq_f32): Likewise.
+       (vldrwq_z_f32): Likewise.
+       (__arm_vld1q_s8): Define intrinsic.
+       (__arm_vld1q_s32): Likewise.
+       (__arm_vld1q_s16): Likewise.
+       (__arm_vld1q_u8): Likewise.
+       (__arm_vld1q_u32): Likewise.
+       (__arm_vld1q_u16): Likewise.
+       (__arm_vldrhq_gather_offset_s32): Likewise.
+       (__arm_vldrhq_gather_offset_s16): Likewise.
+       (__arm_vldrhq_gather_offset_u32): Likewise.
+       (__arm_vldrhq_gather_offset_u16): Likewise.
+       (__arm_vldrhq_gather_offset_z_s32): Likewise.
+       (__arm_vldrhq_gather_offset_z_s16): Likewise.
+       (__arm_vldrhq_gather_offset_z_u32): Likewise.
+       (__arm_vldrhq_gather_offset_z_u16): Likewise.
+       (__arm_vldrhq_gather_shifted_offset_s32): Likewise.
+       (__arm_vldrhq_gather_shifted_offset_s16): Likewise.
+       (__arm_vldrhq_gather_shifted_offset_u32): Likewise.
+       (__arm_vldrhq_gather_shifted_offset_u16): Likewise.
+       (__arm_vldrhq_gather_shifted_offset_z_s32): Likewise.
+       (__arm_vldrhq_gather_shifted_offset_z_s16): Likewise.
+       (__arm_vldrhq_gather_shifted_offset_z_u32): Likewise.
+       (__arm_vldrhq_gather_shifted_offset_z_u16): Likewise.
+       (__arm_vldrhq_s32): Likewise.
+       (__arm_vldrhq_s16): Likewise.
+       (__arm_vldrhq_u32): Likewise.
+       (__arm_vldrhq_u16): Likewise.
+       (__arm_vldrhq_z_s32): Likewise.
+       (__arm_vldrhq_z_s16): Likewise.
+       (__arm_vldrhq_z_u32): Likewise.
+       (__arm_vldrhq_z_u16): Likewise.
+       (__arm_vldrwq_s32): Likewise.
+       (__arm_vldrwq_u32): Likewise.
+       (__arm_vldrwq_z_s32): Likewise.
+       (__arm_vldrwq_z_u32): Likewise.
+       (__arm_vld1q_f32): Likewise.
+       (__arm_vld1q_f16): Likewise.
+       (__arm_vldrwq_f32): Likewise.
+       (__arm_vldrwq_z_f32): Likewise.
+       (__arm_vldrhq_z_f16): Likewise.
+       (__arm_vldrhq_f16): Likewise.
+       (vld1q): Define polymorphic variant.
+       (vldrhq_gather_offset): Likewise.
+       (vldrhq_gather_offset_z): Likewise.
+       (vldrhq_gather_shifted_offset): Likewise.
+       (vldrhq_gather_shifted_offset_z): Likewise.
+       * config/arm/arm_mve_builtins.def (LDRU): Use builtin qualifier.
+       (LDRS): Likewise.
+       (LDRU_Z): Likewise.
+       (LDRS_Z): Likewise.
+       (LDRGU_Z): Likewise.
+       (LDRGU): Likewise.
+       (LDRGS_Z): Likewise.
+       (LDRGS): Likewise.
+       * config/arm/mve.md (MVE_H_ELEM): Define mode iterator.
+       (V_sz_elem1): Likewise.
+       (VLD1Q): Define iterator.
+       (VLDRHGOQ): Likewise.
+       (VLDRHGSOQ): Likewise.
+       (VLDRHQ): Likewise.
+       (VLDRWQ): Likewise.
+       (mve_vldrhq_fv8hf): Define RTL pattern.
+       (mve_vldrhq_gather_offset_<supf><mode>): Likewise.
+       (mve_vldrhq_gather_offset_z_<supf><mode>): Likewise.
+       (mve_vldrhq_gather_shifted_offset_<supf><mode>): Likewise.
+       (mve_vldrhq_gather_shifted_offset_z_<supf><mode>): Likewise.
+       (mve_vldrhq_<supf><mode>): Likewise.
+       (mve_vldrhq_z_fv8hf): Likewise.
+       (mve_vldrhq_z_<supf><mode>): Likewise.
+       (mve_vldrwq_fv4sf): Likewise.
+       (mve_vldrwq_<supf>v4si): Likewise.
+       (mve_vldrwq_z_fv4sf): Likewise.
+       (mve_vldrwq_z_<supf>v4si): Likewise.
+       (mve_vld1q_f<mode>): Define RTL expand pattern.
+       (mve_vld1q_<supf><mode>): Likewise.
+
  2020-03-18  Andre Vieira  <andre.simoesdiasvieira@arm.com>
              Mihail Ionescu  <mihail.ionescu@arm.com>
              Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h

index 4570a0b16c37b11471a61f4b53686945063b4a55..9991e25c8d642c8109ab9ce9f48a818508d7801c 100644 (file)
--- a/gcc/config/arm/arm_mve.h
+++ b/gcc/config/arm/arm_mve.h
@@ -1758,6 +1758,46 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t;
  #define vldrbq_z_u32(__base, __p) __arm_vldrbq_z_u32(__base, __p)
  #define vldrwq_gather_base_z_u32(__addr,  __offset, __p) __arm_vldrwq_gather_base_z_u32(__addr,  __offset, __p)
  #define vldrwq_gather_base_z_s32(__addr,  __offset, __p) __arm_vldrwq_gather_base_z_s32(__addr,  __offset, __p)
+#define vld1q_s8(__base) __arm_vld1q_s8(__base)
+#define vld1q_s32(__base) __arm_vld1q_s32(__base)
+#define vld1q_s16(__base) __arm_vld1q_s16(__base)
+#define vld1q_u8(__base) __arm_vld1q_u8(__base)
+#define vld1q_u32(__base) __arm_vld1q_u32(__base)
+#define vld1q_u16(__base) __arm_vld1q_u16(__base)
+#define vldrhq_gather_offset_s32(__base, __offset) __arm_vldrhq_gather_offset_s32(__base, __offset)
+#define vldrhq_gather_offset_s16(__base, __offset) __arm_vldrhq_gather_offset_s16(__base, __offset)
+#define vldrhq_gather_offset_u32(__base, __offset) __arm_vldrhq_gather_offset_u32(__base, __offset)
+#define vldrhq_gather_offset_u16(__base, __offset) __arm_vldrhq_gather_offset_u16(__base, __offset)
+#define vldrhq_gather_offset_z_s32(__base, __offset, __p) __arm_vldrhq_gather_offset_z_s32(__base, __offset, __p)
+#define vldrhq_gather_offset_z_s16(__base, __offset, __p) __arm_vldrhq_gather_offset_z_s16(__base, __offset, __p)
+#define vldrhq_gather_offset_z_u32(__base, __offset, __p) __arm_vldrhq_gather_offset_z_u32(__base, __offset, __p)
+#define vldrhq_gather_offset_z_u16(__base, __offset, __p) __arm_vldrhq_gather_offset_z_u16(__base, __offset, __p)
+#define vldrhq_gather_shifted_offset_s32(__base, __offset) __arm_vldrhq_gather_shifted_offset_s32(__base, __offset)
+#define vldrhq_gather_shifted_offset_s16(__base, __offset) __arm_vldrhq_gather_shifted_offset_s16(__base, __offset)
+#define vldrhq_gather_shifted_offset_u32(__base, __offset) __arm_vldrhq_gather_shifted_offset_u32(__base, __offset)
+#define vldrhq_gather_shifted_offset_u16(__base, __offset) __arm_vldrhq_gather_shifted_offset_u16(__base, __offset)
+#define vldrhq_gather_shifted_offset_z_s32(__base, __offset, __p) __arm_vldrhq_gather_shifted_offset_z_s32(__base, __offset, __p)
+#define vldrhq_gather_shifted_offset_z_s16(__base, __offset, __p) __arm_vldrhq_gather_shifted_offset_z_s16(__base, __offset, __p)
+#define vldrhq_gather_shifted_offset_z_u32(__base, __offset, __p) __arm_vldrhq_gather_shifted_offset_z_u32(__base, __offset, __p)
+#define vldrhq_gather_shifted_offset_z_u16(__base, __offset, __p) __arm_vldrhq_gather_shifted_offset_z_u16(__base, __offset, __p)
+#define vldrhq_s32(__base) __arm_vldrhq_s32(__base)
+#define vldrhq_s16(__base) __arm_vldrhq_s16(__base)
+#define vldrhq_u32(__base) __arm_vldrhq_u32(__base)
+#define vldrhq_u16(__base) __arm_vldrhq_u16(__base)
+#define vldrhq_z_s32(__base, __p) __arm_vldrhq_z_s32(__base, __p)
+#define vldrhq_z_s16(__base, __p) __arm_vldrhq_z_s16(__base, __p)
+#define vldrhq_z_u32(__base, __p) __arm_vldrhq_z_u32(__base, __p)
+#define vldrhq_z_u16(__base, __p) __arm_vldrhq_z_u16(__base, __p)
+#define vldrwq_s32(__base) __arm_vldrwq_s32(__base)
+#define vldrwq_u32(__base) __arm_vldrwq_u32(__base)
+#define vldrwq_z_s32(__base, __p) __arm_vldrwq_z_s32(__base, __p)
+#define vldrwq_z_u32(__base, __p) __arm_vldrwq_z_u32(__base, __p)
+#define vld1q_f32(__base) __arm_vld1q_f32(__base)
+#define vld1q_f16(__base) __arm_vld1q_f16(__base)
+#define vldrhq_f16(__base) __arm_vldrhq_f16(__base)
+#define vldrhq_z_f16(__base, __p) __arm_vldrhq_z_f16(__base, __p)
+#define vldrwq_f32(__base) __arm_vldrwq_f32(__base)
+#define vldrwq_z_f32(__base, __p) __arm_vldrwq_z_f32(__base, __p)
  #endif
  
  __extension__ extern __inline void
@@ -11443,6 +11483,245 @@ __arm_vldrwq_gather_base_z_u32 (uint32x4_t __addr, const int __offset, mve_pred1
    return __builtin_mve_vldrwq_gather_base_z_uv4si (__addr, __offset, __p);
  }
  
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vld1q_s8 (int8_t const * __base)
+{
+  return __builtin_mve_vld1q_sv16qi ((__builtin_neon_qi *) __base);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vld1q_s32 (int32_t const * __base)
+{
+  return __builtin_mve_vld1q_sv4si ((__builtin_neon_si *) __base);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vld1q_s16 (int16_t const * __base)
+{
+  return __builtin_mve_vld1q_sv8hi ((__builtin_neon_hi *) __base);
+}
+
+__extension__ extern __inline uint8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vld1q_u8 (uint8_t const * __base)
+{
+  return __builtin_mve_vld1q_uv16qi ((__builtin_neon_qi *) __base);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vld1q_u32 (uint32_t const * __base)
+{
+  return __builtin_mve_vld1q_uv4si ((__builtin_neon_si *) __base);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vld1q_u16 (uint16_t const * __base)
+{
+  return __builtin_mve_vld1q_uv8hi ((__builtin_neon_hi *) __base);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_gather_offset_s32 (int16_t const * __base, uint32x4_t __offset)
+{
+  return __builtin_mve_vldrhq_gather_offset_sv4si ((__builtin_neon_hi *) __base, __offset);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_gather_offset_s16 (int16_t const * __base, uint16x8_t __offset)
+{
+  return __builtin_mve_vldrhq_gather_offset_sv8hi ((__builtin_neon_hi *) __base, __offset);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_gather_offset_u32 (uint16_t const * __base, uint32x4_t __offset)
+{
+  return __builtin_mve_vldrhq_gather_offset_uv4si ((__builtin_neon_hi *) __base, __offset);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_gather_offset_u16 (uint16_t const * __base, uint16x8_t __offset)
+{
+  return __builtin_mve_vldrhq_gather_offset_uv8hi ((__builtin_neon_hi *) __base, __offset);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_gather_offset_z_s32 (int16_t const * __base, uint32x4_t __offset, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrhq_gather_offset_z_sv4si ((__builtin_neon_hi *) __base, __offset, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_gather_offset_z_s16 (int16_t const * __base, uint16x8_t __offset, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrhq_gather_offset_z_sv8hi ((__builtin_neon_hi *) __base, __offset, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_gather_offset_z_u32 (uint16_t const * __base, uint32x4_t __offset, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrhq_gather_offset_z_uv4si ((__builtin_neon_hi *) __base, __offset, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_gather_offset_z_u16 (uint16_t const * __base, uint16x8_t __offset, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrhq_gather_offset_z_uv8hi ((__builtin_neon_hi *) __base, __offset, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_gather_shifted_offset_s32 (int16_t const * __base, uint32x4_t __offset)
+{
+  return __builtin_mve_vldrhq_gather_shifted_offset_sv4si ((__builtin_neon_hi *) __base, __offset);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_gather_shifted_offset_s16 (int16_t const * __base, uint16x8_t __offset)
+{
+  return __builtin_mve_vldrhq_gather_shifted_offset_sv8hi ((__builtin_neon_hi *) __base, __offset);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_gather_shifted_offset_u32 (uint16_t const * __base, uint32x4_t __offset)
+{
+  return __builtin_mve_vldrhq_gather_shifted_offset_uv4si ((__builtin_neon_hi *) __base, __offset);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_gather_shifted_offset_u16 (uint16_t const * __base, uint16x8_t __offset)
+{
+  return __builtin_mve_vldrhq_gather_shifted_offset_uv8hi ((__builtin_neon_hi *) __base, __offset);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_gather_shifted_offset_z_s32 (int16_t const * __base, uint32x4_t __offset, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrhq_gather_shifted_offset_z_sv4si ((__builtin_neon_hi *) __base, __offset, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_gather_shifted_offset_z_s16 (int16_t const * __base, uint16x8_t __offset, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrhq_gather_shifted_offset_z_sv8hi ((__builtin_neon_hi *) __base, __offset, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_gather_shifted_offset_z_u32 (uint16_t const * __base, uint32x4_t __offset, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrhq_gather_shifted_offset_z_uv4si ((__builtin_neon_hi *) __base, __offset, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_gather_shifted_offset_z_u16 (uint16_t const * __base, uint16x8_t __offset, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrhq_gather_shifted_offset_z_uv8hi ((__builtin_neon_hi *) __base, __offset, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_s32 (int16_t const * __base)
+{
+  return __builtin_mve_vldrhq_sv4si ((__builtin_neon_hi *) __base);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_s16 (int16_t const * __base)
+{
+  return __builtin_mve_vldrhq_sv8hi ((__builtin_neon_hi *) __base);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_u32 (uint16_t const * __base)
+{
+  return __builtin_mve_vldrhq_uv4si ((__builtin_neon_hi *) __base);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_u16 (uint16_t const * __base)
+{
+  return __builtin_mve_vldrhq_uv8hi ((__builtin_neon_hi *) __base);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_z_s32 (int16_t const * __base, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrhq_z_sv4si ((__builtin_neon_hi *) __base, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_z_s16 (int16_t const * __base, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrhq_z_sv8hi ((__builtin_neon_hi *) __base, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_z_u32 (uint16_t const * __base, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrhq_z_uv4si ((__builtin_neon_hi *) __base, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_z_u16 (uint16_t const * __base, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrhq_z_uv8hi ((__builtin_neon_hi *) __base, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrwq_s32 (int32_t const * __base)
+{
+  return __builtin_mve_vldrwq_sv4si ((__builtin_neon_si *) __base);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrwq_u32 (uint32_t const * __base)
+{
+  return __builtin_mve_vldrwq_uv4si ((__builtin_neon_si *) __base);
+}
+
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrwq_z_s32 (int32_t const * __base, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrwq_z_sv4si ((__builtin_neon_si *) __base, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrwq_z_u32 (uint32_t const * __base, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrwq_z_uv4si ((__builtin_neon_si *) __base, __p);
+}
+
  #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point.  */
  
  __extension__ extern __inline void
@@ -13585,6 +13864,47 @@ __arm_vsubq_m_n_f16 (float16x8_t __inactive, float16x8_t __a, float16_t __b, mve
    return __builtin_mve_vsubq_m_n_fv8hf (__inactive, __a, __b, __p);
  }
  
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vld1q_f32 (float32_t const * __base)
+{
+  return __builtin_mve_vld1q_fv4sf((__builtin_neon_si *) __base);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vld1q_f16 (float16_t const * __base)
+{
+  return __builtin_mve_vld1q_fv8hf((__builtin_neon_hi *) __base);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrwq_f32 (float32_t const * __base)
+{
+  return __builtin_mve_vldrwq_fv4sf((__builtin_neon_si *) __base);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrwq_z_f32 (float32_t const * __base, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrwq_z_fv4sf((__builtin_neon_si *) __base, __p);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_z_f16 (float16_t const * __base, mve_pred16_t __p)
+{
+  return __builtin_mve_vldrhq_z_fv8hf((__builtin_neon_hi *) __base, __p);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_f16 (float16_t const * __base)
+{
+  return __builtin_mve_vldrhq_fv8hf((__builtin_neon_hi *) __base);
+}
  #endif
  
  enum {
@@ -16052,6 +16372,18 @@ extern void *__ARM_undef;
    int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vorrq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \
    int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vorrq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3));})
  
+#define vld1q(p0) __arm_vld1q(p0)
+#define __arm_vld1q(p0) ({ __typeof(p0) __p0 = (p0); \
+  _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
+  int (*)[__ARM_mve_type_int8_t_const_ptr]: __arm_vld1q_s8 (__ARM_mve_coerce(__p0, int8_t const *)), \
+  int (*)[__ARM_mve_type_int16_t_const_ptr]: __arm_vld1q_s16 (__ARM_mve_coerce(__p0, int16_t const *)), \
+  int (*)[__ARM_mve_type_int32_t_const_ptr]: __arm_vld1q_s32 (__ARM_mve_coerce(__p0, int32_t const *)), \
+  int (*)[__ARM_mve_type_uint8_t_const_ptr]: __arm_vld1q_u8 (__ARM_mve_coerce(__p0, uint8_t const *)), \
+  int (*)[__ARM_mve_type_uint16_t_const_ptr]: __arm_vld1q_u16 (__ARM_mve_coerce(__p0, uint16_t const *)), \
+  int (*)[__ARM_mve_type_uint32_t_const_ptr]: __arm_vld1q_u32 (__ARM_mve_coerce(__p0, uint32_t const *)), \
+  int (*)[__ARM_mve_type_float16_t_const_ptr]: __arm_vld1q_f16 (__ARM_mve_coerce(__p0, float16_t const *)), \
+  int (*)[__ARM_mve_type_float32_t_const_ptr]: __arm_vld1q_f32 (__ARM_mve_coerce(__p0, float32_t const *)));})
+
  #else /* MVE Integer.  */
  
  #define vst4q(p0,p1) __arm_vst4q(p0,p1)
@@ -18148,6 +18480,52 @@ extern void *__ARM_undef;
    int (*)[__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_base_p_s32 (p0, p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \
    int (*)[__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_base_p_u32 (p0, p1, __ARM_mve_coerce(__p2, uint32x4_t), p3));})
  
+#define vld1q(p0) __arm_vld1q(p0)
+#define __arm_vld1q(p0) ({ __typeof(p0) __p0 = (p0); \
+  _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
+  int (*)[__ARM_mve_type_int8_t_const_ptr]: __arm_vld1q_s8 (__ARM_mve_coerce(__p0, int8_t const *)), \
+  int (*)[__ARM_mve_type_int16_t_const_ptr]: __arm_vld1q_s16 (__ARM_mve_coerce(__p0, int16_t const *)), \
+  int (*)[__ARM_mve_type_int32_t_const_ptr]: __arm_vld1q_s32 (__ARM_mve_coerce(__p0, int32_t const *)), \
+  int (*)[__ARM_mve_type_uint8_t_const_ptr]: __arm_vld1q_u8 (__ARM_mve_coerce(__p0, uint8_t const *)), \
+  int (*)[__ARM_mve_type_uint16_t_const_ptr]: __arm_vld1q_u16 (__ARM_mve_coerce(__p0, uint16_t const *)), \
+  int (*)[__ARM_mve_type_uint32_t_const_ptr]: __arm_vld1q_u32 (__ARM_mve_coerce(__p0, uint32_t const *)));})
+
+#define vldrhq_gather_offset(p0,p1) __arm_vldrhq_gather_offset(p0,p1)
+#define __arm_vldrhq_gather_offset(p0,p1) ({ __typeof(p0) __p0 = (p0); \
+  __typeof(p1) __p1 = (p1); \
+  _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
+  int (*)[__ARM_mve_type_int16_t_const_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_s16 (__ARM_mve_coerce(__p0, int16_t const *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+  int (*)[__ARM_mve_type_int16_t_const_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_s32 (__ARM_mve_coerce(__p0, int16_t const *), __ARM_mve_coerce(__p1, uint32x4_t)), \
+  int (*)[__ARM_mve_type_uint16_t_const_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_u16 (__ARM_mve_coerce(__p0, uint16_t const *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+  int (*)[__ARM_mve_type_uint16_t_const_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_u32 (__ARM_mve_coerce(__p0, uint16_t const *), __ARM_mve_coerce(__p1, uint32x4_t)));})
+
+#define vldrhq_gather_offset_z(p0,p1,p2) __arm_vldrhq_gather_offset_z(p0,p1,p2)
+#define __arm_vldrhq_gather_offset_z(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
+  __typeof(p1) __p1 = (p1); \
+  _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
+  int (*)[__ARM_mve_type_int16_t_const_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_s16 (__ARM_mve_coerce(__p0, int16_t const *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+  int (*)[__ARM_mve_type_int16_t_const_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_z_s32 (__ARM_mve_coerce(__p0, int16_t const *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
+  int (*)[__ARM_mve_type_uint16_t_const_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_u16 (__ARM_mve_coerce(__p0, uint16_t const *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+  int (*)[__ARM_mve_type_uint16_t_const_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_z_u32 (__ARM_mve_coerce(__p0, uint16_t const *), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
+
+#define vldrhq_gather_shifted_offset(p0,p1) __arm_vldrhq_gather_shifted_offset(p0,p1)
+#define __arm_vldrhq_gather_shifted_offset(p0,p1) ({ __typeof(p0) __p0 = (p0); \
+  __typeof(p1) __p1 = (p1); \
+  _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
+  int (*)[__ARM_mve_type_int16_t_const_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_s16 (__ARM_mve_coerce(__p0, int16_t const *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+  int (*)[__ARM_mve_type_int16_t_const_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_s32 (__ARM_mve_coerce(__p0, int16_t const *), __ARM_mve_coerce(__p1, uint32x4_t)), \
+  int (*)[__ARM_mve_type_uint16_t_const_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_u16 (__ARM_mve_coerce(__p0, uint16_t const *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+  int (*)[__ARM_mve_type_uint16_t_const_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_u32 (__ARM_mve_coerce(__p0, uint16_t const *), __ARM_mve_coerce(__p1, uint32x4_t)));})
+
+#define vldrhq_gather_shifted_offset_z(p0,p1,p2) __arm_vldrhq_gather_shifted_offset_z(p0,p1,p2)
+#define __arm_vldrhq_gather_shifted_offset_z(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
+  __typeof(p1) __p1 = (p1); \
+  _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
+  int (*)[__ARM_mve_type_int16_t_const_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_s16 (__ARM_mve_coerce(__p0, int16_t const *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+  int (*)[__ARM_mve_type_int16_t_const_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_z_s32 (__ARM_mve_coerce(__p0, int16_t const *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
+  int (*)[__ARM_mve_type_uint16_t_const_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_u16 (__ARM_mve_coerce(__p0, uint16_t const *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+  int (*)[__ARM_mve_type_uint16_t_const_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_z_u32 (__ARM_mve_coerce(__p0, uint16_t const *), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
+
  #endif /* MVE Integer.  */
  
  #define vldrbq_gather_offset_z(p0,p1,p2) __arm_vldrbq_gather_offset_z(p0,p1,p2)
diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def

index 0f466e4cec295c1d791d675b52ff15e364d7016e..bafc953a5e5108caa9595ea9189ed1182da2c692 100644 (file)
--- a/gcc/config/arm/arm_mve_builtins.def
+++ b/gcc/config/arm/arm_mve_builtins.def
@@ -709,3 +709,26 @@ VAR3 (LDRGS_Z, vldrbq_gather_offset_z_s, v16qi, v8hi, v4si)
  VAR3 (LDRGU_Z, vldrbq_gather_offset_z_u, v16qi, v8hi, v4si)
  VAR3 (LDRS_Z, vldrbq_z_s, v16qi, v8hi, v4si)
  VAR3 (LDRU_Z, vldrbq_z_u, v16qi, v8hi, v4si)
+VAR3 (LDRU, vld1q_u, v16qi, v8hi, v4si)
+VAR3 (LDRS, vld1q_s, v16qi, v8hi, v4si)
+VAR2 (LDRU_Z, vldrhq_z_u, v8hi, v4si)
+VAR2 (LDRU, vldrhq_u, v8hi, v4si)
+VAR2 (LDRS_Z, vldrhq_z_s, v8hi, v4si)
+VAR2 (LDRS, vldrhq_s, v8hi, v4si)
+VAR2 (LDRS, vld1q_f, v8hf, v4sf)
+VAR2 (LDRGU_Z, vldrhq_gather_shifted_offset_z_u, v8hi, v4si)
+VAR2 (LDRGU_Z, vldrhq_gather_offset_z_u, v8hi, v4si)
+VAR2 (LDRGU, vldrhq_gather_shifted_offset_u, v8hi, v4si)
+VAR2 (LDRGU, vldrhq_gather_offset_u, v8hi, v4si)
+VAR2 (LDRGS_Z, vldrhq_gather_shifted_offset_z_s, v8hi, v4si)
+VAR2 (LDRGS_Z, vldrhq_gather_offset_z_s, v8hi, v4si)
+VAR2 (LDRGS, vldrhq_gather_shifted_offset_s, v8hi, v4si)
+VAR2 (LDRGS, vldrhq_gather_offset_s, v8hi, v4si)
+VAR1 (LDRS, vldrhq_f, v8hf)
+VAR1 (LDRS_Z, vldrhq_z_f, v8hf)
+VAR1 (LDRS, vldrwq_f, v4sf)
+VAR1 (LDRS, vldrwq_s, v4si)
+VAR1 (LDRU, vldrwq_u, v4si)
+VAR1 (LDRS_Z, vldrwq_z_f, v4sf)
+VAR1 (LDRS_Z, vldrwq_z_s, v4si)
+VAR1 (LDRU_Z, vldrwq_z_u, v4si)
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md

index 03a90ab3212954ea881c52e1b80bc69feed59a5d..89ff2e269e5ff0c42954cdd1f773b5456cb6251a 100644 (file)
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -26,6 +26,7 @@
  (define_mode_iterator MVE_3 [V16QI V8HI])
  (define_mode_iterator MVE_2 [V16QI V8HI V4SI])
  (define_mode_iterator MVE_5 [V8HI V4SI])
+(define_mode_iterator MVE_6 [V8HI V4SI])
  
  (define_c_enum "unspec" [VST4Q VRNDXQ_F VRNDQ_F VRNDPQ_F VRNDNQ_F VRNDMQ_F
                          VRNDAQ_F VREV64Q_F VNEGQ_F VDUPQ_N_F VABSQ_F VREV32Q_F
@@ -193,10 +194,13 @@
                          VFMAQ_M_N_F VFMASQ_M_N_F VFMSQ_M_F VMAXNMQ_M_F
                          VMINNMQ_M_F VSUBQ_M_F VSTRWQSB_S VSTRWQSB_U
                          VSTRBQSO_S VSTRBQSO_U VSTRBQ_S VSTRBQ_U VLDRBQGO_S
-                        VLDRBQGO_U VLDRBQ_S VLDRBQ_U VLDRWQGB_S VLDRWQGB_U])
+                        VLDRBQGO_U VLDRBQ_S VLDRBQ_U VLDRWQGB_S VLDRWQGB_U
+                        VLD1Q_F VLD1Q_S VLD1Q_U VLDRHQ_F VLDRHQGO_S
+                        VLDRHQGO_U VLDRHQGSO_S VLDRHQGSO_U VLDRHQ_S VLDRHQ_U
+                        VLDRWQ_F VLDRWQ_S VLDRWQ_U])
  
-(define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF")
-                           (V8HF "V8HI") (V4SF "V4SI")])
+(define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF") (V8HF "V8HI")
+                           (V4SF "V4SI")])
  
  (define_int_attr supf [(VCVTQ_TO_F_S "s") (VCVTQ_TO_F_U "u") (VREV16Q_S "s")
                        (VREV16Q_U "u") (VMVNQ_N_S "s") (VMVNQ_N_U "u")
@@ -348,7 +352,11 @@
                        (VSTRWQSB_S "s") (VSTRWQSB_U "u") (VSTRBQSO_S "s")
                        (VSTRBQSO_U "u") (VSTRBQ_S "s") (VSTRBQ_U "u")
                        (VLDRBQGO_S "s") (VLDRBQGO_U "u") (VLDRBQ_S "s")
-                      (VLDRBQ_U "u") (VLDRWQGB_S "s") (VLDRWQGB_U "u")])
+                      (VLDRBQ_U "u") (VLDRWQGB_S "s") (VLDRWQGB_U "u")
+                      (VLD1Q_S "s") (VLD1Q_U "u") (VLDRHQGO_S "s")
+                      (VLDRHQGO_U "u") (VLDRHQGSO_S "s") (VLDRHQGSO_U "u")
+                      (VLDRHQ_S "s") (VLDRHQ_U "u") (VLDRWQ_S "s")
+                      (VLDRWQ_U "u")])
  
  (define_int_attr mode1 [(VCTP8Q "8") (VCTP16Q "16") (VCTP32Q "32")
                         (VCTP64Q "64") (VCTP8Q_M "8") (VCTP16Q_M "16")
@@ -362,10 +370,12 @@
                                    (V4SI "mve_imm_31")])
  (define_mode_attr MVE_constraint3 [ (V8HI "Rb") (V4SI "Rd")])
  (define_mode_attr MVE_pred3 [ (V8HI "mve_imm_8") (V4SI "mve_imm_16")])
-
  (define_mode_attr MVE_constraint1 [ (V8HI "Ra") (V4SI "Rc")])
  (define_mode_attr MVE_pred1 [ (V8HI "mve_imm_7") (V4SI "mve_imm_15")])
  (define_mode_attr MVE_B_ELEM [ (V16QI "V16QI") (V8HI "V8QI") (V4SI "V4QI")])
+(define_mode_attr MVE_H_ELEM [ (V8HI "V8HI") (V4SI "V4HI")])
+(define_mode_attr V_sz_elem1 [(V16QI "b") (V8HI  "h") (V4SI "w") (V8HF "h")
+                             (V4SF "w")])
  
  (define_int_iterator VCVTQ_TO_F [VCVTQ_TO_F_S VCVTQ_TO_F_U])
  (define_int_iterator VMVNQ_N [VMVNQ_N_U VMVNQ_N_S])
@@ -575,6 +585,11 @@
  (define_int_iterator VLDRBGOQ [VLDRBQGO_S VLDRBQGO_U])
  (define_int_iterator VLDRBQ [VLDRBQ_S VLDRBQ_U])
  (define_int_iterator VLDRWGBQ [VLDRWQGB_S VLDRWQGB_U])
+(define_int_iterator VLD1Q [VLD1Q_S VLD1Q_U])
+(define_int_iterator VLDRHGOQ [VLDRHQGO_S VLDRHQGO_U])
+(define_int_iterator VLDRHGSOQ [VLDRHQGSO_S VLDRHQGSO_U])
+(define_int_iterator VLDRHQ [VLDRHQ_S VLDRHQ_U])
+(define_int_iterator VLDRWQ [VLDRWQ_S VLDRWQ_U])
  
  (define_insn "*mve_mov<mode>"
    [(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w,w,r,w,Us")
@@ -8208,3 +8223,276 @@
     return "";
  }
    [(set_attr "length" "8")])
+
+;;
+;; [vldrhq_f]
+;;
+(define_insn "mve_vldrhq_fv8hf"
+  [(set (match_operand:V8HF 0 "s_register_operand" "=w")
+       (unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us")]
+        VLDRHQ_F))
+  ]
+  "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
+{
+   rtx ops[2];
+   int regno = REGNO (operands[0]);
+   ops[0] = gen_rtx_REG (TImode, regno);
+   ops[1]  = operands[1];
+   output_asm_insn ("vldrh.f16\t%q0, %E1",ops);
+   return "";
+}
+  [(set_attr "length" "4")])
+
+;;
+;; [vldrhq_gather_offset_s vldrhq_gather_offset_u]
+;;
+(define_insn "mve_vldrhq_gather_offset_<supf><mode>"
+  [(set (match_operand:MVE_6 0 "s_register_operand" "=&w")
+       (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us")
+                      (match_operand:MVE_6 2 "s_register_operand" "w")]
+       VLDRHGOQ))
+  ]
+  "TARGET_HAVE_MVE"
+{
+   rtx ops[3];
+   ops[0] = operands[0];
+   ops[1] = operands[1];
+   ops[2] = operands[2];
+   if (!strcmp ("<supf>","s") && <V_sz_elem> == 16)
+     output_asm_insn ("vldrh.u16\t%q0, [%m1, %q2]",ops);
+   else
+     output_asm_insn ("vldrh.<supf><V_sz_elem>\t%q0, [%m1, %q2]",ops);
+   return "";
+}
+  [(set_attr "length" "4")])
+
+;;
+;; [vldrhq_gather_offset_z_s vldrhq_gather_offset_z_u]
+;;
+(define_insn "mve_vldrhq_gather_offset_z_<supf><mode>"
+  [(set (match_operand:MVE_6 0 "s_register_operand" "=&w")
+       (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us")
+                      (match_operand:MVE_6 2 "s_register_operand" "w")
+                      (match_operand:HI 3 "vpr_register_operand" "Up")
+       ]VLDRHGOQ))
+  ]
+  "TARGET_HAVE_MVE"
+{
+   rtx ops[4];
+   ops[0] = operands[0];
+   ops[1] = operands[1];
+   ops[2] = operands[2];
+   ops[3] = operands[3];
+   if (!strcmp ("<supf>","s") && <V_sz_elem> == 16)
+     output_asm_insn ("vpst\n\tvldrht.u16\t%q0, [%m1, %q2]",ops);
+   else
+     output_asm_insn ("vpst\n\tvldrht.<supf><V_sz_elem>\t%q0, [%m1, %q2]",ops);
+   return "";
+}
+ [(set_attr "length" "8")])
+
+;;
+;; [vldrhq_gather_shifted_offset_s vldrhq_gather_shifted_offset_u]
+;;
+(define_insn "mve_vldrhq_gather_shifted_offset_<supf><mode>"
+  [(set (match_operand:MVE_6 0 "s_register_operand" "=&w")
+       (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us")
+                      (match_operand:MVE_6 2 "s_register_operand" "w")]
+       VLDRHGSOQ))
+  ]
+  "TARGET_HAVE_MVE"
+{
+   rtx ops[3];
+   ops[0] = operands[0];
+   ops[1] = operands[1];
+   ops[2] = operands[2];
+      if (!strcmp ("<supf>","s") && <V_sz_elem> == 16)
+     output_asm_insn ("vldrh.u16\t%q0, [%m1, %q2, uxtw #1]",ops);
+   else
+     output_asm_insn ("vldrh.<supf><V_sz_elem>\t%q0, [%m1, %q2, uxtw #1]",ops);
+   return "";
+}
+  [(set_attr "length" "4")])
+
+;;
+;; [vldrhq_gather_shifted_offset_z_s vldrhq_gather_shited_offset_z_u]
+;;
+(define_insn "mve_vldrhq_gather_shifted_offset_z_<supf><mode>"
+  [(set (match_operand:MVE_6 0 "s_register_operand" "=&w")
+       (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us")
+                      (match_operand:MVE_6 2 "s_register_operand" "w")
+                      (match_operand:HI 3 "vpr_register_operand" "Up")
+       ]VLDRHGSOQ))
+  ]
+  "TARGET_HAVE_MVE"
+{
+   rtx ops[4];
+   ops[0] = operands[0];
+   ops[1] = operands[1];
+   ops[2] = operands[2];
+   ops[3] = operands[3];
+   if (!strcmp ("<supf>","s") && <V_sz_elem> == 16)
+     output_asm_insn ("vpst\n\tvldrht.u16\t%q0, [%m1, %q2, uxtw #1]",ops);
+   else
+     output_asm_insn ("vpst\n\tvldrht.<supf><V_sz_elem>\t%q0, [%m1, %q2, uxtw #1]",ops);
+   return "";
+}
+  [(set_attr "length" "8")])
+
+;;
+;;
+;; [vldrhq_s, vldrhq_u]
+;;
+(define_insn "mve_vldrhq_<supf><mode>"
+  [(set (match_operand:MVE_6 0 "s_register_operand" "=w")
+       (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us")]
+        VLDRHQ))
+  ]
+  "TARGET_HAVE_MVE"
+{
+   rtx ops[2];
+   int regno = REGNO (operands[0]);
+   ops[0] = gen_rtx_REG (TImode, regno);
+   ops[1]  = operands[1];
+   output_asm_insn ("vldrh.<supf><V_sz_elem>\t%q0, %E1",ops);
+   return "";
+}
+  [(set_attr "length" "4")])
+
+;;
+;; [vldrhq_z_f]
+;;
+(define_insn "mve_vldrhq_z_fv8hf"
+  [(set (match_operand:V8HF 0 "s_register_operand" "=w")
+       (unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us")
+       (match_operand:HI 2 "vpr_register_operand" "Up")]
+        VLDRHQ_F))
+  ]
+  "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
+{
+   rtx ops[2];
+   int regno = REGNO (operands[0]);
+   ops[0] = gen_rtx_REG (TImode, regno);
+   ops[1]  = operands[1];
+   output_asm_insn ("vpst\n\tvldrht.f16\t%q0, %E1",ops);
+   return "";
+}
+  [(set_attr "length" "8")])
+
+;;
+;; [vldrhq_z_s vldrhq_z_u]
+;;
+(define_insn "mve_vldrhq_z_<supf><mode>"
+  [(set (match_operand:MVE_6 0 "s_register_operand" "=w")
+       (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us")
+       (match_operand:HI 2 "vpr_register_operand" "Up")]
+        VLDRHQ))
+  ]
+  "TARGET_HAVE_MVE"
+{
+   rtx ops[2];
+   int regno = REGNO (operands[0]);
+   ops[0] = gen_rtx_REG (TImode, regno);
+   ops[1]  = operands[1];
+   output_asm_insn ("vpst\n\tvldrht.<supf><V_sz_elem>\t%q0, %E1",ops);
+   return "";
+}
+  [(set_attr "length" "8")])
+
+;;
+;; [vldrwq_f]
+;;
+(define_insn "mve_vldrwq_fv4sf"
+  [(set (match_operand:V4SF 0 "s_register_operand" "=w")
+       (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us")]
+        VLDRWQ_F))
+  ]
+  "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
+{
+   rtx ops[2];
+   int regno = REGNO (operands[0]);
+   ops[0] = gen_rtx_REG (TImode, regno);
+   ops[1]  = operands[1];
+   output_asm_insn ("vldrw.f32\t%q0, %E1",ops);
+   return "";
+}
+  [(set_attr "length" "4")])
+
+;;
+;; [vldrwq_s vldrwq_u]
+;;
+(define_insn "mve_vldrwq_<supf>v4si"
+  [(set (match_operand:V4SI 0 "s_register_operand" "=w")
+       (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us")]
+        VLDRWQ))
+  ]
+  "TARGET_HAVE_MVE"
+{
+   rtx ops[2];
+   int regno = REGNO (operands[0]);
+   ops[0] = gen_rtx_REG (TImode, regno);
+   ops[1]  = operands[1];
+   output_asm_insn ("vldrw.<supf>32\t%q0, %E1",ops);
+   return "";
+}
+  [(set_attr "length" "4")])
+
+;;
+;; [vldrwq_z_f]
+;;
+(define_insn "mve_vldrwq_z_fv4sf"
+  [(set (match_operand:V4SF 0 "s_register_operand" "=w")
+       (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us")
+       (match_operand:HI 2 "vpr_register_operand" "Up")]
+        VLDRWQ_F))
+  ]
+  "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
+{
+   rtx ops[2];
+   int regno = REGNO (operands[0]);
+   ops[0] = gen_rtx_REG (TImode, regno);
+   ops[1]  = operands[1];
+   output_asm_insn ("vpst\n\tvldrwt.f32\t%q0, %E1",ops);
+   return "";
+}
+  [(set_attr "length" "8")])
+
+;;
+;; [vldrwq_z_s vldrwq_z_u]
+;;
+(define_insn "mve_vldrwq_z_<supf>v4si"
+  [(set (match_operand:V4SI 0 "s_register_operand" "=w")
+       (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us")
+       (match_operand:HI 2 "vpr_register_operand" "Up")]
+        VLDRWQ))
+  ]
+  "TARGET_HAVE_MVE"
+{
+   rtx ops[2];
+   int regno = REGNO (operands[0]);
+   ops[0] = gen_rtx_REG (TImode, regno);
+   ops[1]  = operands[1];
+   output_asm_insn ("vpst\n\tvldrwt.<supf>32\t%q0, %E1",ops);
+   return "";
+}
+  [(set_attr "length" "8")])
+
+(define_expand "mve_vld1q_f<mode>"
+  [(match_operand:MVE_0 0 "s_register_operand")
+   (unspec:MVE_0 [(match_operand:<MVE_CNVT> 1 "memory_operand")] VLD1Q_F)
+  ]
+  "TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT"
+{
+  emit_insn (gen_mve_vldr<V_sz_elem1>q_f<mode>(operands[0],operands[1]));
+  DONE;
+})
+
+(define_expand "mve_vld1q_<supf><mode>"
+  [(match_operand:MVE_2 0 "s_register_operand")
+   (unspec:MVE_2 [(match_operand:MVE_2 1 "memory_operand")] VLD1Q)
+  ]
+  "TARGET_HAVE_MVE"
+{
+  emit_insn (gen_mve_vldr<V_sz_elem1>q_<supf><mode>(operands[0],operands[1]));
+  DONE;
+})
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog

index 451f0eee2768aa464eb9019e216697a06d230b2c..a86d0e66aaca6647c3a959e1678da63d4e6f6845 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,48 @@
+2020-03-18  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+            Mihail Ionescu  <mihail.ionescu@arm.com>
+            Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
+
+       * gcc.target/arm/mve/intrinsics/vld1q_f16.c: New test.
+       * gcc.target/arm/mve/intrinsics/vld1q_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vld1q_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vld1q_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vld1q_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vld1q_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vld1q_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vld1q_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vldrhq_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vldrhq_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vldrhq_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vldrhq_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vldrhq_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vldrwq_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vldrwq_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vldrwq_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c: Likewise.
+
  2020-03-18  Andre Vieira  <andre.simoesdiasvieira@arm.com>
              Mihail Ionescu  <mihail.ionescu@arm.com>
              Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f16.c

new file mode 100644 (file)

index 0000000..91e39f5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f16.c
@@ -0,0 +1,22 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16_t const * base)
+{
+  return vld1q_f16 (base);
+}
+
+/* { dg-final { scan-assembler "vldrh.f16"  }  } */
+
+float16x8_t
+foo1 (float16_t const * base)
+{
+  return vld1q (base);
+}
+
+/* { dg-final { scan-assembler "vldrh.f16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f32.c

new file mode 100644 (file)

index 0000000..0ef33ad
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f32.c
@@ -0,0 +1,22 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32_t const * base)
+{
+  return vld1q_f32 (base);
+}
+
+/* { dg-final { scan-assembler "vldrw.f32"  }  } */
+
+float32x4_t
+foo1 (float32_t const * base)
+{
+  return vld1q (base);
+}
+
+/* { dg-final { scan-assembler "vldrw.f32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s16.c

new file mode 100644 (file)

index 0000000..adf2f5b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s16.c
@@ -0,0 +1,22 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16_t const * base)
+{
+  return vld1q_s16 (base);
+}
+
+/* { dg-final { scan-assembler "vldrh.s16"  }  } */
+
+int16x8_t
+foo1 (int16_t const * base)
+{
+  return vld1q (base);
+}
+
+/* { dg-final { scan-assembler "vldrh.s16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s32.c

new file mode 100644 (file)

index 0000000..94df0b4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s32.c
@@ -0,0 +1,22 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32_t const * base)
+{
+  return vld1q_s32 (base);
+}
+
+/* { dg-final { scan-assembler "vldrw.s32"  }  } */
+
+int32x4_t
+foo1 (int32_t const * base)
+{
+  return vld1q (base);
+}
+
+/* { dg-final { scan-assembler "vldrw.s32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s8.c

new file mode 100644 (file)

index 0000000..9a8b304
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s8.c
@@ -0,0 +1,22 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8_t const * base)
+{
+  return vld1q_s8 (base);
+}
+
+/* { dg-final { scan-assembler "vldrb.s8"  }  } */
+
+int8x16_t
+foo1 (int8_t const * base)
+{
+  return vld1q (base);
+}
+
+/* { dg-final { scan-assembler "vldrb.s8"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u16.c

new file mode 100644 (file)

index 0000000..4c5916b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u16.c
@@ -0,0 +1,22 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16_t const * base)
+{
+  return vld1q_u16 (base);
+}
+
+/* { dg-final { scan-assembler "vldrh.u16"  }  } */
+
+uint16x8_t
+foo1 (uint16_t const * base)
+{
+  return vld1q (base);
+}
+
+/* { dg-final { scan-assembler "vldrh.u16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u32.c

new file mode 100644 (file)

index 0000000..8f4d521
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u32.c
@@ -0,0 +1,22 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint32_t const * base)
+{
+  return vld1q_u32 (base);
+}
+
+/* { dg-final { scan-assembler "vldrw.u32"  }  } */
+
+uint32x4_t
+foo1 (uint32_t const * base)
+{
+  return vld1q (base);
+}
+
+/* { dg-final { scan-assembler "vldrw.u32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u8.c

new file mode 100644 (file)

index 0000000..3804394
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u8.c
@@ -0,0 +1,22 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint8x16_t
+foo (uint8_t const * base)
+{
+  return vld1q_u8 (base);
+}
+
+/* { dg-final { scan-assembler "vldrb.u8"  }  } */
+
+uint8x16_t
+foo1 (uint8_t const * base)
+{
+  return vld1q (base);
+}
+
+/* { dg-final { scan-assembler "vldrb.u8"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_f16.c

new file mode 100644 (file)

index 0000000..ef7b5d4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_f16.c
@@ -0,0 +1,14 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16_t const * base)
+{
+  return vldrhq_f16 (base);
+}
+
+/* { dg-final { scan-assembler "vldrh.f16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c

new file mode 100644 (file)

index 0000000..72e5ae2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c
@@ -0,0 +1,22 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16_t const * base, uint16x8_t offset)
+{
+  return vldrhq_gather_offset_s16 (base, offset);
+}
+
+/* { dg-final { scan-assembler "vldrh.u16"  }  } */
+
+int16x8_t
+foo1 (int16_t const * base, uint16x8_t offset)
+{
+  return vldrhq_gather_offset (base, offset);
+}
+
+/* { dg-final { scan-assembler "vldrh.u16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c

new file mode 100644 (file)

index 0000000..14a850a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c
@@ -0,0 +1,22 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int16_t const * base, uint32x4_t offset)
+{
+  return vldrhq_gather_offset_s32 (base, offset);
+}
+
+/* { dg-final { scan-assembler "vldrh.s32"  }  } */
+
+int32x4_t
+foo1 (int16_t const * base, uint32x4_t offset)
+{
+  return vldrhq_gather_offset (base, offset);
+}
+
+/* { dg-final { scan-assembler "vldrh.s32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c

new file mode 100644 (file)

index 0000000..6e8f881
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c
@@ -0,0 +1,22 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16_t const * base, uint16x8_t offset)
+{
+  return vldrhq_gather_offset_u16 (base, offset);
+}
+
+/* { dg-final { scan-assembler "vldrh.u16"  }  } */
+
+uint16x8_t
+foo1 (uint16_t const * base, uint16x8_t offset)
+{
+  return vldrhq_gather_offset (base, offset);
+}
+
+/* { dg-final { scan-assembler "vldrh.u16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c

new file mode 100644 (file)

index 0000000..5e18f63
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c
@@ -0,0 +1,22 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint16_t const * base, uint32x4_t offset)
+{
+  return vldrhq_gather_offset_u32 (base, offset);
+}
+
+/* { dg-final { scan-assembler "vldrh.u32"  }  } */
+
+uint32x4_t
+foo1 (uint16_t const * base, uint32x4_t offset)
+{
+  return vldrhq_gather_offset (base, offset);
+}
+
+/* { dg-final { scan-assembler "vldrh.u32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c

new file mode 100644 (file)

index 0000000..625a818
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c
@@ -0,0 +1,22 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16_t const * base, uint16x8_t offset, mve_pred16_t p)
+{
+  return vldrhq_gather_offset_z_s16 (base, offset, p);
+}
+
+/* { dg-final { scan-assembler "vldrht.u16"  }  } */
+
+int16x8_t
+foo1 (int16_t const * base, uint16x8_t offset, mve_pred16_t p)
+{
+  return vldrhq_gather_offset_z (base, offset, p);
+}
+
+/* { dg-final { scan-assembler "vldrht.u16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c

new file mode 100644 (file)

index 0000000..bb10468
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c
@@ -0,0 +1,22 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int16_t const * base, uint32x4_t offset, mve_pred16_t p)
+{
+  return vldrhq_gather_offset_z_s32 (base, offset, p);
+}
+
+/* { dg-final { scan-assembler "vldrht.s32"  }  } */
+
+int32x4_t
+foo1 (int16_t const * base, uint32x4_t offset, mve_pred16_t p)
+{
+  return vldrhq_gather_offset_z (base, offset, p);
+}
+
+/* { dg-final { scan-assembler "vldrht.s32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c

new file mode 100644 (file)

index 0000000..8a69d05
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c
@@ -0,0 +1,22 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16_t const * base, uint16x8_t offset, mve_pred16_t p)
+{
+  return vldrhq_gather_offset_z_u16 (base, offset, p);
+}
+
+/* { dg-final { scan-assembler "vldrht.u16"  }  } */
+
+uint16x8_t
+foo1 (uint16_t const * base, uint16x8_t offset, mve_pred16_t p)
+{
+  return vldrhq_gather_offset_z (base, offset, p);
+}
+
+/* { dg-final { scan-assembler "vldrht.u16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c

new file mode 100644 (file)

index 0000000..f88dc5e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c
@@ -0,0 +1,22 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint16_t const * base, uint32x4_t offset, mve_pred16_t p)
+{
+  return vldrhq_gather_offset_z_u32 (base, offset, p);
+}
+
+/* { dg-final { scan-assembler "vldrht.u32"  }  } */
+
+uint32x4_t
+foo1 (uint16_t const * base, uint32x4_t offset, mve_pred16_t p)
+{
+  return vldrhq_gather_offset_z (base, offset, p);
+}
+
+/* { dg-final { scan-assembler "vldrht.u32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s16.c

new file mode 100644 (file)

index 0000000..b82323f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s16.c
@@ -0,0 +1,22 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16_t const * base, uint16x8_t offset)
+{
+  return vldrhq_gather_shifted_offset_s16 (base, offset);
+}
+
+/* { dg-final { scan-assembler "vldrh.u16"  }  } */
+
+int16x8_t
+foo1 (int16_t const * base, uint16x8_t offset)
+{
+  return vldrhq_gather_shifted_offset (base, offset);
+}
+
+/* { dg-final { scan-assembler "vldrh.u16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s32.c

new file mode 100644 (file)

index 0000000..15f496c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s32.c
@@ -0,0 +1,22 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int16_t const * base, uint32x4_t offset)
+{
+  return vldrhq_gather_shifted_offset_s32 (base, offset);
+}
+
+/* { dg-final { scan-assembler "vldrh.s32"  }  } */
+
+int32x4_t
+foo1 (int16_t const * base, uint32x4_t offset)
+{
+  return vldrhq_gather_shifted_offset (base, offset);
+}
+
+/* { dg-final { scan-assembler "vldrh.s32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u16.c

new file mode 100644 (file)

index 0000000..ccf93d4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u16.c
@@ -0,0 +1,22 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16_t const * base, uint16x8_t offset)
+{
+  return vldrhq_gather_shifted_offset_u16 (base, offset);
+}
+
+/* { dg-final { scan-assembler "vldrh.u16"  }  } */
+
+uint16x8_t
+foo1 (uint16_t const * base, uint16x8_t offset)
+{
+  return vldrhq_gather_shifted_offset (base, offset);
+}
+
+/* { dg-final { scan-assembler "vldrh.u16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u32.c

new file mode 100644 (file)

index 0000000..558893c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u32.c
@@ -0,0 +1,22 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint16_t const * base, uint32x4_t offset)
+{
+  return vldrhq_gather_shifted_offset_u32 (base, offset);
+}
+
+/* { dg-final { scan-assembler "vldrh.u32"  }  } */
+
+uint32x4_t
+foo1 (uint16_t const * base, uint32x4_t offset)
+{
+  return vldrhq_gather_shifted_offset (base, offset);
+}
+
+/* { dg-final { scan-assembler "vldrh.u32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s16.c

new file mode 100644 (file)

index 0000000..c2f5429
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s16.c
@@ -0,0 +1,22 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16_t const * base, uint16x8_t offset, mve_pred16_t p)
+{
+  return vldrhq_gather_shifted_offset_z_s16 (base, offset, p);
+}
+
+/* { dg-final { scan-assembler "vldrht.u16"  }  } */
+
+int16x8_t
+foo1 (int16_t const * base, uint16x8_t offset, mve_pred16_t p)
+{
+  return vldrhq_gather_shifted_offset_z (base, offset, p);
+}
+
+/* { dg-final { scan-assembler "vldrht.u16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s32.c

new file mode 100644 (file)

index 0000000..2565592
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s32.c
@@ -0,0 +1,22 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int16_t const * base, uint32x4_t offset, mve_pred16_t p)
+{
+  return vldrhq_gather_shifted_offset_z_s32 (base, offset, p);
+}
+
+/* { dg-final { scan-assembler "vldrht.s32"  }  } */
+
+int32x4_t
+foo1 (int16_t const * base, uint32x4_t offset, mve_pred16_t p)
+{
+  return vldrhq_gather_shifted_offset_z (base, offset, p);
+}
+
+/* { dg-final { scan-assembler "vldrht.s32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u16.c

new file mode 100644 (file)

index 0000000..3ade339
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u16.c
@@ -0,0 +1,22 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16_t const * base, uint16x8_t offset, mve_pred16_t p)
+{
+  return vldrhq_gather_shifted_offset_z_u16 (base, offset, p);
+}
+
+/* { dg-final { scan-assembler "vldrht.u16"  }  } */
+
+uint16x8_t
+foo1 (uint16_t const * base, uint16x8_t offset, mve_pred16_t p)
+{
+  return vldrhq_gather_shifted_offset_z (base, offset, p);
+}
+
+/* { dg-final { scan-assembler "vldrht.u16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u32.c

new file mode 100644 (file)

index 0000000..c37203b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u32.c
@@ -0,0 +1,22 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint16_t const * base, uint32x4_t offset, mve_pred16_t p)
+{
+  return vldrhq_gather_shifted_offset_z_u32 (base, offset, p);
+}
+
+/* { dg-final { scan-assembler "vldrht.u32"  }  } */
+
+uint32x4_t
+foo1 (uint16_t const * base, uint32x4_t offset, mve_pred16_t p)
+{
+  return vldrhq_gather_shifted_offset_z (base, offset, p);
+}
+
+/* { dg-final { scan-assembler "vldrht.u32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s16.c

new file mode 100644 (file)

index 0000000..dd5b7c0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s16.c
@@ -0,0 +1,14 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16_t const * base)
+{
+  return vldrhq_s16 (base);
+}
+
+/* { dg-final { scan-assembler "vldrh.s16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s32.c

new file mode 100644 (file)

index 0000000..ee3613c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s32.c
@@ -0,0 +1,14 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int16_t const * base)
+{
+  return vldrhq_s32 (base);
+}
+
+/* { dg-final { scan-assembler "vldrh.s32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u16.c

new file mode 100644 (file)

index 0000000..460931f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u16.c
@@ -0,0 +1,14 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16_t const * base)
+{
+  return vldrhq_u16 (base);
+}
+
+/* { dg-final { scan-assembler "vldrh.u16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u32.c

new file mode 100644 (file)

index 0000000..1cd04f5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u32.c
@@ -0,0 +1,14 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint16_t const * base)
+{
+  return vldrhq_u32 (base);
+}
+
+/* { dg-final { scan-assembler "vldrh.u32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c

new file mode 100644 (file)

index 0000000..3ea1db7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c
@@ -0,0 +1,14 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16_t const * base, mve_pred16_t p)
+{
+  return vldrhq_z_f16 (base, p);
+}
+
+/* { dg-final { scan-assembler "vldrht.f16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c

new file mode 100644 (file)

index 0000000..9a700ab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c
@@ -0,0 +1,14 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16_t const * base, mve_pred16_t p)
+{
+  return vldrhq_z_s16 (base, p);
+}
+
+/* { dg-final { scan-assembler "vldrht.s16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c

new file mode 100644 (file)

index 0000000..729b627
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c
@@ -0,0 +1,14 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int16_t const * base, mve_pred16_t p)
+{
+  return vldrhq_z_s32 (base, p);
+}
+
+/* { dg-final { scan-assembler "vldrht.s32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c

new file mode 100644 (file)

index 0000000..a511e3a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c
@@ -0,0 +1,14 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16_t const * base, mve_pred16_t p)
+{
+  return vldrhq_z_u16 (base, p);
+}
+
+/* { dg-final { scan-assembler "vldrht.u16"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c

new file mode 100644 (file)

index 0000000..7b0a9a2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c
@@ -0,0 +1,14 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint16_t const * base, mve_pred16_t p)
+{
+  return vldrhq_z_u32 (base, p);
+}
+
+/* { dg-final { scan-assembler "vldrht.u32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_f32.c

new file mode 100644 (file)

index 0000000..eea4571
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_f32.c
@@ -0,0 +1,14 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32_t const * base)
+{
+  return vldrwq_f32 (base);
+}
+
+/* { dg-final { scan-assembler "vldrw.f32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_s32.c

new file mode 100644 (file)

index 0000000..4f18dc6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_s32.c
@@ -0,0 +1,14 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32_t const * base)
+{
+  return vldrwq_s32 (base);
+}
+
+/* { dg-final { scan-assembler "vldrw.s32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_u32.c

new file mode 100644 (file)

index 0000000..b3672e5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_u32.c
@@ -0,0 +1,14 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint32_t const * base)
+{
+  return vldrwq_u32 (base);
+}
+
+/* { dg-final { scan-assembler "vldrw.u32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c

new file mode 100644 (file)

index 0000000..0af5f96
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c
@@ -0,0 +1,14 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32_t const * base, mve_pred16_t p)
+{
+  return vldrwq_z_f32 (base, p);
+}
+
+/* { dg-final { scan-assembler "vldrwt.f32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c

new file mode 100644 (file)

index 0000000..a8589cd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c
@@ -0,0 +1,14 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32_t const * base, mve_pred16_t p)
+{
+  return vldrwq_z_s32 (base, p);
+}
+
+/* { dg-final { scan-assembler "vldrwt.s32"  }  } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c

new file mode 100644 (file)

index 0000000..d5fa5cf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c
@@ -0,0 +1,14 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint32_t const * base, mve_pred16_t p)
+{
+  return vldrwq_z_u32 (base, p);
+}
+
+/* { dg-final { scan-assembler "vldrwt.u32"  }  } */
author	Srinath Parvathaneni <srinath.parvathaneni@arm.com>
	Wed, 18 Mar 2020 18:48:05 +0000 (18:48 +0000)
committer	Kyrylo Tkachov <kyrylo.tkachov@arm.com>
	Wed, 18 Mar 2020 18:48:05 +0000 (18:48 +0000)
gcc/ChangeLog		patch \| blob \| history
gcc/config/arm/arm_mve.h		patch \| blob \| history
gcc/config/arm/arm_mve_builtins.def		patch \| blob \| history
gcc/config/arm/mve.md		patch \| blob \| history
gcc/testsuite/ChangeLog		patch \| blob \| history
gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f16.c	[new file with mode: 0644]	patch \| blob
gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f32.c	[new file with mode: 0644]	patch \| blob
gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s16.c	[new file with mode: 0644]	patch \| blob
gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s32.c	[new file with mode: 0644]	patch \| blob
gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s8.c	[new file with mode: 0644]	patch \| blob
gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u16.c	[new file with mode: 0644]	patch \| blob
gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u32.c	[new file with mode: 0644]	patch \| blob
gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u8.c	[new file with mode: 0644]	patch \| blob
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_f16.c	[new file with mode: 0644]	patch \| blob
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c	[new file with mode: 0644]	patch \| blob
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c	[new file with mode: 0644]	patch \| blob
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c	[new file with mode: 0644]	patch \| blob
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c	[new file with mode: 0644]	patch \| blob
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c	[new file with mode: 0644]	patch \| blob
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c	[new file with mode: 0644]	patch \| blob
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c	[new file with mode: 0644]	patch \| blob
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c	[new file with mode: 0644]	patch \| blob
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s16.c	[new file with mode: 0644]	patch \| blob
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s32.c	[new file with mode: 0644]	patch \| blob
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u16.c	[new file with mode: 0644]	patch \| blob
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u32.c	[new file with mode: 0644]	patch \| blob
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s16.c	[new file with mode: 0644]	patch \| blob
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s32.c	[new file with mode: 0644]	patch \| blob
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u16.c	[new file with mode: 0644]	patch \| blob
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u32.c	[new file with mode: 0644]	patch \| blob
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s16.c	[new file with mode: 0644]	patch \| blob
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s32.c	[new file with mode: 0644]	patch \| blob
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u16.c	[new file with mode: 0644]	patch \| blob
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u32.c	[new file with mode: 0644]	patch \| blob
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c	[new file with mode: 0644]	patch \| blob
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c	[new file with mode: 0644]	patch \| blob
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c	[new file with mode: 0644]	patch \| blob
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c	[new file with mode: 0644]	patch \| blob
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c	[new file with mode: 0644]	patch \| blob
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_f32.c	[new file with mode: 0644]	patch \| blob
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_s32.c	[new file with mode: 0644]	patch \| blob
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_u32.c	[new file with mode: 0644]	patch \| blob
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c	[new file with mode: 0644]	patch \| blob
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c	[new file with mode: 0644]	patch \| blob
gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c	[new file with mode: 0644]	patch \| blob