vec_y.push_back(ez->literal());
}
+ void extendSignalWidthUnary(std::vector<int> &vec_a, std::vector<int> &vec_y, RTLIL::Cell *cell)
+ {
+ bool is_signed = cell->parameters.count("\\A_SIGNED") > 0 && cell->parameters["\\A_SIGNED"].as_bool();
+ while (vec_a.size() < vec_y.size())
+ vec_a.push_back(is_signed && vec_a.size() > 0 ? vec_a.back() : ez->FALSE);
+ while (vec_y.size() < vec_a.size())
+ vec_y.push_back(ez->literal());
+ }
+
bool importCell(RTLIL::Cell *cell, int timestep = -1)
{
if (cell->type == "$_AND_" || cell->type == "$_OR_" || cell->type == "$_XOR_" ||
if (cell->type == "$pos" || cell->type == "$neg") {
std::vector<int> a = importSigSpec(cell->connections.at("\\A"), timestep);
std::vector<int> y = importSigSpec(cell->connections.at("\\Y"), timestep);
+ extendSignalWidthUnary(a, y, cell);
if (cell->type == "$pos") {
ez->assume(ez->vec_eq(a, y));
} else {
+#define GENERATE_BINARY_OPS
+#define GENERATE_UNARY_OPS
+
#include <sys/stat.h>
#include <sys/types.h>
#include <stdio.h>
{
mkdir("rtl", 0777);
- // generate test cases for binary operators
-
+#ifdef GENERATE_BINARY_OPS
for (int ai = 0; ai < sizeof(arg_types)/sizeof(arg_types[0]); ai++)
for (int bi = 0; bi < sizeof(arg_types)/sizeof(arg_types[0]); bi++)
for (int yi = 0; yi < sizeof(arg_types)/sizeof(arg_types[0]); yi++)
fprintf(f, "endmodule\n");
fclose(f);
}
+#endif
- // generate test cases for unary operators
-
+#ifdef GENERATE_UNARY_OPS
for (int ai = 0; ai < sizeof(arg_types)/sizeof(arg_types[0]); ai++)
for (int yi = 0; yi < sizeof(arg_types)/sizeof(arg_types[0]); yi++)
for (int oi = 0; oi < sizeof(unary_ops)/sizeof(unary_ops[0]); oi++)
FILE *f = fopen(buffer, "w");
fprintf(f, "module unary_ops_%02d%02d%02d(a, b, y);\n", ai, yi, oi);
fprintf(f, "%s;\n", a_decl.c_str());
+ fprintf(f, "input b;\n");
fprintf(f, "%s;\n", y_decl.c_str());
fprintf(f, "assign %s = %s %s;\n", y_ref.c_str(),
unary_ops[oi], a_ref.c_str());
fprintf(f, "endmodule\n");
fclose(f);
}
+#endif
return 0;
}