Use RenameClockDomains decorator instead of add_submodule

diff --git a/milkymist/dvisampler/analysis.py b/milkymist/dvisampler/analysis.py
index bf1663f5f8aaa64aaab528c1b94fd4ae617da403..c7d247862a07ac7859e97c5aa13346acf11f17a4 100644 (file)
--- a/milkymist/dvisampler/analysis.py
+++ b/milkymist/dvisampler/analysis.py
@@ -137,8 +137,9 @@ class FrameExtraction(Module, AutoCSR):
                        vsync_r.eq(self.vsync)
                ]
 
-               fifo = AsyncFIFO(layout_len(frame_layout), 512)
-               self.add_submodule(fifo, {"write": "pix", "read": "sys"})
+               fifo = RenameClockDomains(AsyncFIFO(layout_len(frame_layout), 512),
+                       {"write": "pix", "read": "sys"})
+               self.submodules += fifo
                self.comb += [
                        fifo.we.eq(fifo_stb),
                        fifo.din.eq(fifo_in.raw_bits()),

diff --git a/milkymist/dvisampler/chansync.py b/milkymist/dvisampler/chansync.py
index ce6bbaca1965e5e03efa3ad053612abcfd877bed..272408e1d867a7dc0b5ec5b37276b8cb7a04a61a 100644 (file)
--- a/milkymist/dvisampler/chansync.py
+++ b/milkymist/dvisampler/chansync.py
@@ -56,8 +56,8 @@ class ChanSync(Module, AutoCSR):
 
                        ###
                
-                       syncbuffer = _SyncBuffer(layout_len(channel_layout), depth)
-                       self.add_submodule(syncbuffer, "pix")
+                       syncbuffer = RenameClockDomains(_SyncBuffer(layout_len(channel_layout), depth), "pix")
+                       self.submodules += syncbuffer
                        self.comb += [
                                syncbuffer.din.eq(data_in.raw_bits()),
                                data_out.raw_bits().eq(syncbuffer.dout)

diff --git a/milkymist/dvisampler/debug.py b/milkymist/dvisampler/debug.py
index 52df4e6d95b3a82487c888a773428459972adba2..39326640ac9154004af10cdebd2920e064548b61 100644 (file)
--- a/milkymist/dvisampler/debug.py
+++ b/milkymist/dvisampler/debug.py
@@ -25,8 +25,9 @@ class RawDVISampler(Module, AutoCSR):
                        self.data0_cap.serdesstrobe.eq(self.clocking.serdesstrobe)
                ]
 
-               fifo = AsyncFIFO(10, 256)
-               self.add_submodule(fifo, {"write": "pix", "read": "sys"})
+               fifo = RenameClockDomains(AsyncFIFO(10, 256),
+                       {"write": "pix", "read": "sys"})
+               self.submodules += fifo
                self.comb += [
                        fifo.din.eq(self.data0_cap.d),
                        fifo.we.eq(1)

diff --git a/milkymist/framebuffer/lib.py b/milkymist/framebuffer/lib.py
index 18b0be40f71c5655be36e01d10f77ac9eaeed656..81bfa44b947badf142dba90a8f1c72b9b331fa86 100644 (file)
--- a/milkymist/framebuffer/lib.py
+++ b/milkymist/framebuffer/lib.py
@@ -128,8 +128,9 @@ class FIFO(Module):
                ###
 
                data_width = 2+2*3*bpc_dac
-               fifo = AsyncFIFO(data_width, 512)
-               self.add_submodule(fifo, {"write": "sys", "read": "vga"})
+               fifo = RenameClockDomains(AsyncFIFO(data_width, 512),
+                       {"write": "sys", "read": "vga"})
+               self.submodules += fifo
                fifo_in = self.dac.payload
                fifo_out = Record(dac_layout)
                self.comb += [

diff --git a/tb/dvisampler/chansync.py b/tb/dvisampler/chansync.py
index cc38e07e2c130d240e55c53f9c7a0456c6023b59..9a8fbf779c306f63d453f9755ca0874c690c13ed 100644 (file)
--- a/tb/dvisampler/chansync.py
+++ b/tb/dvisampler/chansync.py
@@ -7,8 +7,7 @@ class TB(Module):
        def __init__(self, test_seq_it):
                self.test_seq_it = test_seq_it
 
-               self.chansync = ChanSync()
-               self.add_submodule(self.chansync, {"pix": "sys"})
+               self.submodules.chansync = RenameClockDomains(ChanSync(), {"pix": "sys"})
                self.comb += self.chansync.valid_i.eq(1)
 
        def do_simulation(self, s):