mem: Wakeup sleeping CPUs without caches on LLSC

For systems without caches, the LLSC code does not get snoops for
wake-ups. We add the LLSC code in the abstract memory to do the job
for us.

diff --git a/src/arch/null/cpu_dummy.hh b/src/arch/null/cpu_dummy.hh
index ed6f6d1d6ab97f62818391abf8192a4349af6bae..f546b4141b1c9ae774735aa8864c970420c144a3 100644 (file)
--- a/src/arch/null/cpu_dummy.hh
+++ b/src/arch/null/cpu_dummy.hh
@@ -47,6 +47,7 @@ class BaseCPU
   public:
     static int numSimulatedInsts() { return 0; }
     static int numSimulatedOps() { return 0; }
+    static void wakeup() { ; }
 };
 
 #endif // __ARCH_NULL_CPU_DUMMY_HH__

diff --git a/src/mem/abstract_mem.cc b/src/mem/abstract_mem.cc
index a169243e9ed9b1dea9f9acb88936038e8406ec54..98f03b9afc4dc01f70018172ead717b0745e6389 100644 (file)
--- a/src/mem/abstract_mem.cc
+++ b/src/mem/abstract_mem.cc
@@ -44,6 +44,8 @@
 
 #include "arch/registers.hh"
 #include "config/the_isa.hh"
+#include "cpu/base.hh"
+#include "cpu/thread_context.hh"
 #include "debug/LLSC.hh"
 #include "debug/MemoryAccess.hh"
 #include "mem/abstract_mem.hh"
@@ -260,6 +262,12 @@ AbstractMemory::checkLockedAddrList(PacketPtr pkt)
             if (i->addr == paddr) {
                 DPRINTF(LLSC, "Erasing lock record: context %d addr %#x\n",
                         i->contextId, paddr);
+                // For ARM, a spinlock would typically include a Wait
+                // For Event (WFE) to conserve energy. The ARMv8
+                // architecture specifies that an event is
+                // automatically generated when clearing the exclusive
+                // monitor to wake up the processor in WFE.
+                system()->getThreadContext(i->contextId)->getCpuPtr()->wakeup();
                 i = lockedAddrList.erase(i);
             } else {
                 i++;