struct pipe_vertex_element vertex_element[PIPE_MAX_ATTRIBS];
int vertex_element_count;
+ struct pipe_stencil_ref stencil_ref;
+
/* Bitmask of dirty state objects. */
uint32_t dirty_state;
/* Flag indicating whether or not the HW is dirty. */
struct r300_screen* r300screen = r300_screen(r300->context.screen);
struct pipe_framebuffer_state* fb =
(struct pipe_framebuffer_state*)r300->fb_state.state;
+ struct pipe_stencil_ref stencil_ref = r300->stencil_ref;
CS_LOCALS(r300);
BEGIN_CS(r300screen->caps->is_r500 ? 8 : 6);
OUT_CS(0);
}
- OUT_CS(dsa->stencil_ref_mask);
+ OUT_CS(dsa->stencil_ref_mask | stencil_ref.ref_value[0]);
if (r300screen->caps->is_r500) {
- OUT_CS_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf);
+ OUT_CS_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf | stencil_ref.ref_value[1]);
}
END_CS;
}
(r300_translate_stencil_op(state->stencil[0].zfail_op) <<
R300_S_FRONT_ZFAIL_OP_SHIFT);
- dsa->stencil_ref_mask = (state->stencil[0].ref_value) |
+ dsa->stencil_ref_mask =
(state->stencil[0].valuemask << R300_STENCILMASK_SHIFT) |
(state->stencil[0].writemask << R300_STENCILWRITEMASK_SHIFT);
if (caps->is_r500)
{
dsa->z_buffer_control |= R500_STENCIL_REFMASK_FRONT_BACK;
- dsa->stencil_ref_bf = (state->stencil[1].ref_value) |
+ dsa->stencil_ref_bf =
(state->stencil[1].valuemask <<
R300_STENCILMASK_SHIFT) |
(state->stencil[1].writemask <<
FREE(state);
}
+static void r300_set_stencil_ref(struct pipe_context* pipe,
+ const struct pipe_stencil_ref* sr)
+{
+ struct r300_context* r300 = r300_context(pipe);
+ r300->stencil_ref = *sr;
+ r300->dsa_state.dirty = TRUE;
+}
+
static void
r300_set_framebuffer_state(struct pipe_context* pipe,
const struct pipe_framebuffer_state* state)
r300->context.bind_depth_stencil_alpha_state = r300_bind_dsa_state;
r300->context.delete_depth_stencil_alpha_state = r300_delete_dsa_state;
+ r300->context.set_stencil_ref = r300_set_stencil_ref;
+
r300->context.set_framebuffer_state = r300_set_framebuffer_state;
r300->context.create_fs_state = r300_create_fs_state;