xilinx_{7series,ultrascale}: run `report_methodology`.

This can expose important timing issues, such as #301.

diff --git a/nmigen/vendor/xilinx_7series.py b/nmigen/vendor/xilinx_7series.py
index 899defc320fc7486019e0fc5e67dcb8b3cc3fbc6..50f66367de5a677096d9b93b57b479eb6eb0db74 100644 (file)
--- a/nmigen/vendor/xilinx_7series.py
+++ b/nmigen/vendor/xilinx_7series.py
@@ -38,6 +38,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
         * ``{{name}}_clock_utilization.rpt``:  Vivado report.
         * ``{{name}}_route_status.rpt``: Vivado report.
         * ``{{name}}_drc.rpt``: Vivado report.
+        * ``{{name}}_methodology.rpt``: Vivado report.
         * ``{{name}}_timing.rpt``: Vivado report.
         * ``{{name}}_power.rpt``: Vivado report.
         * ``{{name}}_route.dcp``: Vivado design checkpoint.
@@ -116,6 +117,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
             write_checkpoint -force {{name}}_route.dcp
             report_route_status -file {{name}}_route_status.rpt
             report_drc -file {{name}}_drc.rpt
+            report_methodology -file {{name}}_methodology.rpt
             report_timing_summary -datasheet -max_paths 10 -file {{name}}_timing.rpt
             report_power -file {{name}}_power.rpt
             {{get_override("script_before_bitstream")|default("# (script_before_bitstream placeholder)")}}

diff --git a/nmigen/vendor/xilinx_ultrascale.py b/nmigen/vendor/xilinx_ultrascale.py
index 15aadd4cc41750679769fdd180983e61d35a7fd6..74d5986d75c92679475e1a9533c090735f54dd6f 100644 (file)
--- a/nmigen/vendor/xilinx_ultrascale.py
+++ b/nmigen/vendor/xilinx_ultrascale.py
@@ -38,6 +38,7 @@ class XilinxUltraScalePlatform(TemplatedPlatform):
         * ``{{name}}_clock_utilization.rpt``:  Vivado report.
         * ``{{name}}_route_status.rpt``: Vivado report.
         * ``{{name}}_drc.rpt``: Vivado report.
+        * ``{{name}}_methodology.rpt``: Vivado report.
         * ``{{name}}_timing.rpt``: Vivado report.
         * ``{{name}}_power.rpt``: Vivado report.
         * ``{{name}}_route.dcp``: Vivado design checkpoint.
@@ -116,6 +117,7 @@ class XilinxUltraScalePlatform(TemplatedPlatform):
             write_checkpoint -force {{name}}_route.dcp
             report_route_status -file {{name}}_route_status.rpt
             report_drc -file {{name}}_drc.rpt
+            report_methodology -file {{name}}_methodology.rpt
             report_timing_summary -datasheet -max_paths 10 -file {{name}}_timing.rpt
             report_power -file {{name}}_power.rpt
             {{get_override("script_before_bitstream")|default("# (script_before_bitstream placeholder)")}}