re PR target/17984 (Recent peephole2:s may cause internal compiler errors (2))

	PR target/17984
	* config/cris/cris.md (asrandb, asrandw, lsrandb, lsrandw): Apply
	trunc_int_for_mode for constants used in shortened mode.

From-SVN: r89011

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 647941c6ecdc54ea8114f9d6d1b88d6760754d05..036c72f18c501eb8332894d2fbd47ae14cd39924 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2004-10-14  Hans-Peter Nilsson  <hp@axis.com>
+
+       PR target/17984
+       * config/cris/cris.md (asrandb, asrandw, lsrandb, lsrandw): Apply
+       trunc_int_for_mode for constants used in shortened mode.
+
 2004-10-13  Richard Henderson  <rth@redhat.com>
 
         PR c/17384

diff --git a/gcc/config/cris/cris.md b/gcc/config/cris/cris.md
index 1e925dbf4baf159f7d49a363f456c3cd83398c65..d4e4a5a5eed64f5696e7a8ac25383e0300c22916 100644 (file)
--- a/gcc/config/cris/cris.md
+++ b/gcc/config/cris/cris.md
@@ -4717,9 +4717,12 @@
    && (INTVAL (operands[2])
          & ((HOST_WIDE_INT) -1 << (32 - INTVAL (operands[1])))) == 0"
   [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1)))
-   (set (match_dup 3) (and:QI (match_dup 3) (match_dup 2)))]
+   (set (match_dup 3) (and:QI (match_dup 3) (match_dup 4)))]
   ;; FIXME: CC0 is valid except for the M bit.
-  "operands[3] = gen_rtx_REG (QImode, REGNO (operands[0]));")
+{
+  operands[3] = gen_rtx_REG (QImode, REGNO (operands[0]));
+  operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), QImode));
+})
 
 (define_peephole2 ; asrandw (peephole casesi+32)
   [(set (match_operand:SI 0 "register_operand" "")
@@ -4735,9 +4738,12 @@
    && (INTVAL (operands[2])
        & ((HOST_WIDE_INT) -1 << (32 - INTVAL (operands[1])))) == 0"
   [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1)))
-   (set (match_dup 3) (and:HI (match_dup 3) (match_dup 2)))]
+   (set (match_dup 3) (and:HI (match_dup 3) (match_dup 4)))]
   ;; FIXME: CC0 is valid except for the M bit.
-  "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));")
+{
+  operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
+  operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), HImode));
+})
 
 (define_peephole2 ; lsrandb (peephole casesi+33)
   [(set (match_operand:SI 0 "register_operand" "")
@@ -4749,9 +4755,12 @@
    && INTVAL (operands[2]) < 255
    && INTVAL (operands[1]) > 23"
   [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1)))
-   (set (match_dup 3) (and:QI (match_dup 3) (match_dup 2)))]
+   (set (match_dup 3) (and:QI (match_dup 3) (match_dup 4)))]
   ;; FIXME: CC0 is valid except for the M bit.
-  "operands[3] = gen_rtx_REG (QImode, REGNO (operands[0]));")
+{
+  operands[3] = gen_rtx_REG (QImode, REGNO (operands[0]));
+  operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), QImode));
+})
 
 (define_peephole2 ; lsrandw (peephole casesi+34)
   [(set (match_operand:SI 0 "register_operand" "")
@@ -4763,9 +4772,12 @@
    && INTVAL (operands[2]) != 255
    && INTVAL (operands[1]) > 15"
   [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1)))
-   (set (match_dup 3) (and:HI (match_dup 3) (match_dup 2)))]
+   (set (match_dup 3) (and:HI (match_dup 3) (match_dup 4)))]
   ;; FIXME: CC0 is valid except for the M bit.
-  "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));")
+{
+  operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
+  operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), HImode));
+})
 \f
 
 ;; Change