* variable, and thus qualify for being in def[].
*/
if (inst->dst.file == GRF &&
- v->alloc.sizes[inst->dst.reg] == 1 &&
+ alloc.sizes[inst->dst.reg] == 1 &&
!inst->predicate) {
for (int c = 0; c < 4; c++) {
if (inst->dst.writemask & (1 << c)) {
}
}
-vec4_live_variables::vec4_live_variables(vec4_visitor *v, cfg_t *cfg)
- : v(v), cfg(cfg)
+vec4_live_variables::vec4_live_variables(const simple_allocator &alloc,
+ cfg_t *cfg)
+ : alloc(alloc), cfg(cfg)
{
mem_ctx = ralloc_context(NULL);
- num_vars = v->alloc.count * 4;
+ num_vars = alloc.count * 4;
block_data = rzalloc_array(mem_ctx, struct block_data, cfg->num_blocks);
bitset_words = BITSET_WORDS(num_vars);
* The control flow-aware analysis was done at a channel level, while at
* this point we're distilling it down to vgrfs.
*/
- this->live_intervals = new(mem_ctx) vec4_live_variables(this, cfg);
+ this->live_intervals = new(mem_ctx) vec4_live_variables(alloc, cfg);
foreach_block (block, cfg) {
struct block_data *bd = &live_intervals->block_data[block->num];
public:
DECLARE_RALLOC_CXX_OPERATORS(vec4_live_variables)
- vec4_live_variables(vec4_visitor *v, cfg_t *cfg);
+ vec4_live_variables(const simple_allocator &alloc, cfg_t *cfg);
~vec4_live_variables();
int num_vars;
void setup_def_use();
void compute_live_variables();
- vec4_visitor *v;
+ const simple_allocator &alloc;
cfg_t *cfg;
void *mem_ctx;
};