// sized chunks, feed it those one at a time while oring them in.
for (int i = 0; i < Chunks; i++) {
unsigned shift = i * ChunkSize * 8;
- flags |= (std::bitset<NumFlags>(setFlags >> shift) << shift);
+ flags |= (std::bitset<Num_Flags>(setFlags >> shift) << shift);
}
}
Source('legiontrace.cc')
SimObject('DummyChecker.py')
+SimObject('StaticInstFlags.py')
Source('checker/cpu.cc')
Source('dummy_checker.cc')
DebugFlag('Checker')
--- /dev/null
+# Copyright (c) 2003-2005 The Regents of The University of Michigan
+# Copyright (c) 2013 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+
+from m5.params import *
+
+# Set of boolean static instruction properties.
+#
+# Notes:
+# - The IsInteger and IsFloating flags are based on the class of registers
+# accessed by the instruction. Although most instructions will have exactly
+# one of these two flags set, it is possible for an instruction to have
+# neither (e.g., direct unconditional branches, memory barriers) or both
+# (e.g., an FP/int conversion).
+# - If IsMemRef is set, then exactly one of IsLoad or IsStore will be set.
+# - If IsControl is set, then exactly one of IsDirectControl or IsIndirect
+# Control will be set, and exactly one of IsCondControl or IsUncondControl
+# will be set.
+# - IsSerializing, IsMemBarrier, and IsWriteBarrier are implemented as flags
+# since in the current model there's no other way for instructions to inject
+# behavior into the pipeline outside of fetch. Once we go to an exec-in-exec
+# CPU model we should be able to get rid of these flags and implement this
+# behavior via the execute() methods.
+
+class StaticInstFlags(Enum):
+ wrapper_name = 'StaticInstFlags'
+ wrapper_is_struct = True
+ enum_name = 'Flags'
+
+ vals = [
+ 'IsNop', # Is a no-op (no effect at all).
+
+ 'IsInteger', # References integer regs.
+ 'IsFloating', # References FP regs.
+ 'IsCC', # References CC regs.
+
+ 'IsMemRef', # References memory (load, store, or prefetch)
+ 'IsLoad', # Reads from memory (load or prefetch).
+ 'IsStore', # Writes to memory.
+ 'IsStoreConditional', # Store conditional instruction.
+ 'IsIndexed', # Accesses memory with an indexed address
+ # computation
+ 'IsInstPrefetch', # Instruction-cache prefetch.
+ 'IsDataPrefetch', # Data-cache prefetch.
+
+ 'IsControl', # Control transfer instruction.
+ 'IsDirectControl', # PC relative control transfer.
+ 'IsIndirectControl',# Register indirect control transfer.
+ 'IsCondControl', # Conditional control transfer.
+ 'IsUncondControl', # Unconditional control transfer.
+ 'IsCall', # Subroutine call.
+ 'IsReturn', # Subroutine return.
+
+ 'IsCondDelaySlot', # Conditional Delay-Slot Instruction
+
+ 'IsThreadSync', # Thread synchronization operation.
+
+ 'IsSerializing', # Serializes pipeline: won't execute until all
+ # older instructions have committed.
+ 'IsSerializeBefore',
+ 'IsSerializeAfter',
+ 'IsMemBarrier', # Is a memory barrier
+ 'IsWriteBarrier', # Is a write barrier
+ 'IsReadBarrier', # Is a read barrier
+ 'IsERET', # <- Causes the IFU to stall (MIPS ISA)
+
+ 'IsNonSpeculative', # Should not be executed speculatively
+ 'IsQuiesce', # Is a quiesce instruction
+
+ 'IsIprAccess', # Accesses IPRs
+ 'IsUnverifiable', # Can't be verified by a checker
+
+ 'IsSyscall', # Causes a system call to be emulated in syscall
+ # emulation mode.
+
+ # Flags for microcode
+ 'IsMacroop', # Is a macroop containing microops
+ 'IsMicroop', # Is a microop
+ 'IsDelayedCommit', # This microop doesn't commit right away
+ 'IsLastMicroop', # This microop ends a microop sequence
+ 'IsFirstMicroop', # This microop begins a microop sequence
+ # This flag doesn't do anything yet
+ 'IsMicroBranch', # This microop branches within the microcode for
+ # a macroop
+ 'IsDspOp',
+ 'IsSquashAfter' # Squash all uncommitted state after executed
+ ]
return *cachedDisassembly;
}
+
+void
+StaticInst::printFlags(std::ostream &outs,
+ const std::string &separator) const
+{
+ bool printed_a_flag = false;
+
+ for (unsigned int flag = IsNop; flag < Num_Flags; flag++) {
+ if (flags[flag]) {
+ if (printed_a_flag)
+ outs << separator;
+
+ outs << FlagsStrings[flag];
+ printed_a_flag = true;
+ }
+ }
+}
#include "cpu/op_class.hh"
#include "cpu/static_inst_fwd.hh"
#include "cpu/thread_context.hh"
+#include "enums/StaticInstFlags.hh"
#include "sim/fault_fwd.hh"
// forward declarations
* solely on these flags can process instructions without being
* recompiled for multiple ISAs.
*/
-class StaticInst : public RefCounted
+class StaticInst : public RefCounted, public StaticInstFlags
{
public:
/// Binary extended machine instruction type.
MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs
};
- /// Set of boolean static instruction properties.
- ///
- /// Notes:
- /// - The IsInteger and IsFloating flags are based on the class of
- /// registers accessed by the instruction. Although most
- /// instructions will have exactly one of these two flags set, it
- /// is possible for an instruction to have neither (e.g., direct
- /// unconditional branches, memory barriers) or both (e.g., an
- /// FP/int conversion).
- /// - If IsMemRef is set, then exactly one of IsLoad or IsStore
- /// will be set.
- /// - If IsControl is set, then exactly one of IsDirectControl or
- /// IsIndirect Control will be set, and exactly one of
- /// IsCondControl or IsUncondControl will be set.
- /// - IsSerializing, IsMemBarrier, and IsWriteBarrier are
- /// implemented as flags since in the current model there's no
- /// other way for instructions to inject behavior into the
- /// pipeline outside of fetch. Once we go to an exec-in-exec CPU
- /// model we should be able to get rid of these flags and
- /// implement this behavior via the execute() methods.
- ///
- enum Flags {
- IsNop, ///< Is a no-op (no effect at all).
-
- IsInteger, ///< References integer regs.
- IsFloating, ///< References FP regs.
- IsCC, ///< References CC regs.
-
- IsMemRef, ///< References memory (load, store, or prefetch).
- IsLoad, ///< Reads from memory (load or prefetch).
- IsStore, ///< Writes to memory.
- IsStoreConditional, ///< Store conditional instruction.
- IsIndexed, ///< Accesses memory with an indexed address computation
- IsInstPrefetch, ///< Instruction-cache prefetch.
- IsDataPrefetch, ///< Data-cache prefetch.
-
- IsControl, ///< Control transfer instruction.
- IsDirectControl, ///< PC relative control transfer.
- IsIndirectControl, ///< Register indirect control transfer.
- IsCondControl, ///< Conditional control transfer.
- IsUncondControl, ///< Unconditional control transfer.
- IsCall, ///< Subroutine call.
- IsReturn, ///< Subroutine return.
-
- IsCondDelaySlot,///< Conditional Delay-Slot Instruction
-
- IsThreadSync, ///< Thread synchronization operation.
-
- IsSerializing, ///< Serializes pipeline: won't execute until all
- /// older instructions have committed.
- IsSerializeBefore,
- IsSerializeAfter,
- IsMemBarrier, ///< Is a memory barrier
- IsWriteBarrier, ///< Is a write barrier
- IsReadBarrier, ///< Is a read barrier
- IsERET, /// <- Causes the IFU to stall (MIPS ISA)
-
- IsNonSpeculative, ///< Should not be executed speculatively
- IsQuiesce, ///< Is a quiesce instruction
-
- IsIprAccess, ///< Accesses IPRs
- IsUnverifiable, ///< Can't be verified by a checker
-
- IsSyscall, ///< Causes a system call to be emulated in syscall
- /// emulation mode.
-
- //Flags for microcode
- IsMacroop, ///< Is a macroop containing microops
- IsMicroop, ///< Is a microop
- IsDelayedCommit, ///< This microop doesn't commit right away
- IsLastMicroop, ///< This microop ends a microop sequence
- IsFirstMicroop, ///< This microop begins a microop sequence
- //This flag doesn't do anything yet
- IsMicroBranch, ///< This microop branches within the microcode for a macroop
- IsDspOp,
- IsSquashAfter, ///< Squash all uncommitted state after executed
- NumFlags
- };
-
protected:
/// Flag values for this instruction.
- std::bitset<NumFlags> flags;
+ std::bitset<Num_Flags> flags;
/// See opClass().
OpClass _opClass;
virtual const std::string &disassemble(Addr pc,
const SymbolTable *symtab = 0) const;
+ /**
+ * Print a separator separated list of this instruction's set flag
+ * names on the given stream.
+ */
+ void printFlags(std::ostream &outs, const std::string &separator) const;
+
/// Return name of machine instruction
std::string getName() { return mnemonic; }
};
# Note that we wrap the enum in a class/struct to act as a namespace,
# so that the enum strings can be brief w/o worrying about collisions.
def cxx_decl(cls, code):
- name = cls.__name__
+ wrapper_name = cls.wrapper_name
+ wrapper = 'struct' if cls.wrapper_is_struct else 'namespace'
+ name = cls.__name__ if cls.enum_name is None else cls.enum_name
+ idem_macro = '__ENUM__%s__%s__' % (wrapper_name, name)
+
code('''\
-#ifndef __ENUM__${name}__
-#define __ENUM__${name}__
+#ifndef $idem_macro
+#define $idem_macro
-namespace Enums {
+$wrapper $wrapper_name {
enum $name {
''')
code.indent(2)
code('$val = ${{cls.map[val]}},')
code('Num_$name = ${{len(cls.vals)}}')
code.dedent(2)
- code('''\
- };
-extern const char *${name}Strings[Num_${name}];
-}
+ code(' };')
-#endif // __ENUM__${name}__
-''')
+ if cls.wrapper_is_struct:
+ code(' static const char *${name}Strings[Num_${name}];')
+ code('};')
+ else:
+ code('extern const char *${name}Strings[Num_${name}];')
+ code('}')
+
+ code()
+ code('#endif // $idem_macro')
def cxx_def(cls, code):
- name = cls.__name__
- code('''\
-#include "enums/$name.hh"
-namespace Enums {
- const char *${name}Strings[Num_${name}] =
- {
-''')
- code.indent(2)
+ wrapper_name = cls.wrapper_name
+ file_name = cls.__name__
+ name = cls.__name__ if cls.enum_name is None else cls.enum_name
+
+ code('#include "enums/$file_name.hh"')
+ if cls.wrapper_is_struct:
+ code('const char *${wrapper_name}::${name}Strings'
+ '[Num_${name}] =')
+ else:
+ code('namespace Enums {')
+ code.indent(1)
+ code(' const char *${name}Strings[Num_${name}] =')
+
+ code('{')
+ code.indent(1)
for val in cls.vals:
code('"$val",')
- code.dedent(2)
- code('''
- };
-} // namespace Enums
-''')
+ code.dedent(1)
+ code('};')
+
+ if not cls.wrapper_is_struct:
+ code('} // namespace $wrapper_name')
+ code.dedent(1)
def swig_decl(cls, code):
name = cls.__name__
__metaclass__ = MetaEnum
vals = []
+ # The name of the wrapping namespace or struct
+ wrapper_name = 'Enums'
+
+ # If true, the enum is wrapped in a struct rather than a namespace
+ wrapper_is_struct = False
+
+ # If not None, use this as the enum name rather than this class name
+ enum_name = None
+
def __init__(self, value):
if value not in self.map:
raise TypeError, "Enum param got bad value '%s' (not in %s)" \
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