+++ /dev/null
-/**
- *
- * ExampleBlackParrotSystem For Simulating With Litex
- *
- */
-
-`include "bsg_noc_links.vh"
-
-module ExampleBlackParrotSystem
- import bp_common_pkg::*;
- import bp_common_aviary_pkg::*;
- import bp_be_pkg::*;
- import bp_common_rv64_pkg::*;
- import bp_cce_pkg::*;
- import bp_cfg_link_pkg::*;
- #(parameter bp_cfg_e cfg_p = e_bp_single_core_cfg // Replaced by the flow with a specific bp_cfg
- `declare_bp_proc_params(cfg_p)
- `declare_bp_me_if_widths(paddr_width_p, cce_block_width_p, num_lce_p, lce_assoc_p)
-
- // Tracing parameters
- , parameter calc_trace_p = 1
- , parameter cce_trace_p = 0
- , parameter cmt_trace_p = 0
- , parameter dram_trace_p = 0
- , parameter skip_init_p = 0
-
- , parameter mem_load_p = 1
- , parameter mem_file_p = "prog.mem"
- , parameter mem_cap_in_bytes_p = 2**20
- , parameter [paddr_width_p-1:0] mem_offset_p = paddr_width_p'(32'h8000_0000)
-
- )
- (input clk_i
- , input reset_i
- //Wishbone interface
- , input [63:0] wbm_dat_i
- , output [63:0] wbm_dat_o
- , input wbm_ack_i
- // , input wbm_err_i
- // , input wbm_rty_i
- , output [36:0] wbm_adr_o //TODO parametrize this
- , output wbm_stb_o
- , output wbm_cyc_o
- , output wbm_sel_o //TODO: how many bits ? check 3.5 table 3-1
- , output wbm_we_o
- , output [2:0] wbm_cti_o //TODO: hardwire in Litex
- , output [1:0] wbm_bte_o //TODO: hardwire in Litex
- , output all_finished_debug_o //SC_add
- , output core_passed_debug
- , output core_failed_debug
- , input [3:0] interrupts
- );
-
-`declare_bsg_ready_and_link_sif_s(mem_noc_flit_width_p, bsg_ready_and_link_sif_s);
-`declare_bp_me_if(paddr_width_p, cce_block_width_p, num_lce_p, lce_assoc_p)
-
-bsg_ready_and_link_sif_s cmd_link_li, cmd_link_lo;
-bsg_ready_and_link_sif_s resp_link_li, resp_link_lo;
-
-bsg_ready_and_link_sif_s mem_cmd_link_li, mem_cmd_link_lo, mem_resp_link_li, mem_resp_link_lo;
-bsg_ready_and_link_sif_s cfg_cmd_link_li, cfg_cmd_link_lo, cfg_resp_link_li, cfg_resp_link_lo;
-
-assign mem_cmd_link_li = cmd_link_li;
-assign cfg_cmd_link_li = '{ready_and_rev: cmd_link_li.ready_and_rev, default: '0};
-assign cmd_link_lo = '{data: cfg_cmd_link_lo.data
- ,v : cfg_cmd_link_lo.v
- ,ready_and_rev: mem_cmd_link_lo.ready_and_rev
- };
-
-assign mem_resp_link_li = '{ready_and_rev: resp_link_li.ready_and_rev, default: '0};
-assign cfg_resp_link_li = resp_link_li;
-assign resp_link_lo = '{data: mem_resp_link_lo.data
- ,v : mem_resp_link_lo.v
- ,ready_and_rev: cfg_resp_link_lo.ready_and_rev
- };
-
-bp_cce_mem_msg_s mem_resp_li;
-logic mem_resp_v_li, mem_resp_ready_lo;
-bp_cce_mem_msg_s mem_cmd_lo;
-logic mem_cmd_v_lo, mem_cmd_yumi_li;
-
-bp_cce_mem_msg_s dram_resp_lo;
-logic dram_resp_v_lo, dram_resp_ready_li;
-bp_cce_mem_msg_s dram_cmd_li;
-logic dram_cmd_v_li, dram_cmd_yumi_lo;
-
-bp_cce_mem_msg_s host_resp_lo;
-logic host_resp_v_lo, host_resp_ready_li;
-bp_cce_mem_msg_s host_cmd_li;
-logic host_cmd_v_li, host_cmd_yumi_lo;
-
-bp_cce_mem_msg_s cfg_cmd_lo;
-logic cfg_cmd_v_lo, cfg_cmd_ready_li;
-bp_cce_mem_msg_s cfg_resp_li;
-logic cfg_resp_v_li, cfg_resp_ready_lo;
-
-logic [mem_noc_cord_width_p-1:0] dram_cord_lo, mmio_cord_lo, host_cord_lo;
-logic [num_core_p-1:0][mem_noc_cord_width_p-1:0] tile_cord_lo;
-logic [num_mem_p-1:0][mem_noc_cord_width_p-1:0] mem_cord_lo;
-
-assign mmio_cord_lo[0+:mem_noc_x_cord_width_p] = mmio_x_pos_p;
-assign mmio_cord_lo[mem_noc_x_cord_width_p+:mem_noc_y_cord_width_p] = '0;
-assign dram_cord_lo[0+:mem_noc_x_cord_width_p] = mem_noc_x_dim_p+2;
-assign dram_cord_lo[mem_noc_x_cord_width_p+:mem_noc_y_cord_width_p] = '0;
-assign host_cord_lo[0+:mem_noc_x_cord_width_p] = mem_noc_x_dim_p+2;
-assign host_cord_lo[mem_noc_x_cord_width_p+:mem_noc_y_cord_width_p] = '0;
-
-for (genvar j = 0; j < mem_noc_y_dim_p; j++)
- begin : y
- for (genvar i = 0; i < mem_noc_x_dim_p; i++)
- begin : x
- localparam idx = j*mem_noc_x_dim_p + i;
- assign tile_cord_lo[idx][0+:mem_noc_x_cord_width_p] = i+1;
- assign tile_cord_lo[idx][mem_noc_x_cord_width_p+:mem_noc_y_cord_width_p] = j+1;
- end
- end
-for (genvar i = 0; i < num_mem_p; i++)
- begin : x
- assign mem_cord_lo[i][0+:mem_noc_x_cord_width_p] = i;
- assign mem_cord_lo[i][mem_noc_x_cord_width_p+:mem_noc_y_cord_width_p] = '0;
- end
-
-// Chip
-bp_chip
- #(.cfg_p(cfg_p))
- chip
- (.core_clk_i(clk_i)
- ,.core_reset_i(reset_i)
-
- ,.coh_clk_i(clk_i)
- ,.coh_reset_i(reset_i)
-
- ,.mem_clk_i(clk_i)
- ,.mem_reset_i(reset_i)
-
- ,.mem_cord_i(mem_cord_lo)
- ,.tile_cord_i(tile_cord_lo)
- ,.dram_cord_i(dram_cord_lo)
- ,.mmio_cord_i(mmio_cord_lo)
- ,.host_cord_i(host_cord_lo)
-
- ,.prev_cmd_link_i('0)
- ,.prev_cmd_link_o()
-
- ,.prev_resp_link_i('0)
- ,.prev_resp_link_o()
-
- ,.next_cmd_link_i(cmd_link_lo)
- ,.next_cmd_link_o(cmd_link_li)
-
- ,.next_resp_link_i(resp_link_lo)
- ,.next_resp_link_o(resp_link_li)
- );
-
- bind bp_be_top
- bp_nonsynth_commit_tracer
- #(.cfg_p(cfg_p))
- commit_tracer
- (.clk_i(clk_i & (ExampleBlackParrotSystem.cmt_trace_p == 1))
- ,.reset_i(reset_i)
-
- ,.mhartid_i('0)
-
- ,.commit_v_i(be_calculator.instret_mem3_o)
- ,.commit_pc_i(be_calculator.pc_mem3_o)
- ,.commit_instr_i(be_calculator.instr_mem3_o)
-
- ,.rd_w_v_i(be_calculator.int_regfile.rd_w_v_i)
- ,.rd_addr_i(be_calculator.int_regfile.rd_addr_i)
- ,.rd_data_i(be_calculator.int_regfile.rd_data_i)
- );
-
-
-/* bind bp_be_top
- bp_be_nonsynth_tracer
- #(.cfg_p(cfg_p))
- tracer
- // Workaround for verilator binding by accident
- // TODO: Figure out why tracing is always enabled
- (.clk_i(clk_i & (ExampleBlackParrotSystem.calc_trace_p == 1))
- ,.reset_i(reset_i)
-
- ,.mhartid_i(be_calculator.proc_cfg.core_id)
-
- ,.issue_pkt_i(be_calculator.issue_pkt)
- ,.issue_pkt_v_i(be_calculator.issue_pkt_v_i)
-
- ,.fe_nop_v_i(be_calculator.fe_nop_v)
- ,.be_nop_v_i(be_calculator.be_nop_v)
- ,.me_nop_v_i(be_calculator.me_nop_v)
- ,.dispatch_pkt_i(be_calculator.dispatch_pkt)
-
- ,.ex1_br_tgt_i(be_calculator.calc_status.int1_br_tgt)
- ,.ex1_btaken_i(be_calculator.calc_status.int1_btaken)
- ,.iwb_result_i(be_calculator.comp_stage_n[3])
- ,.fwb_result_i(be_calculator.comp_stage_n[4])
-
- ,.cmt_trace_exc_i(be_calculator.exc_stage_n[1+:5])
-
- ,.trap_v_i(be_mem.csr.trap_v_o)
- ,.mtvec_i(be_mem.csr.mtvec_n)
- ,.mtval_i(be_mem.csr.mtval_n[0+:vaddr_width_p])
- ,.ret_v_i(be_mem.csr.ret_v_o)
- ,.mepc_i(be_mem.csr.mepc_n[0+:vaddr_width_p])
- ,.mcause_i(be_mem.csr.mcause_n)
-
- ,.priv_mode_i(be_mem.csr.priv_mode_n)
- ,.mpp_i(be_mem.csr.mstatus_n.mpp)
- );
-*/
-/*bind bp_be_top
- bp_be_nonsynth_perf
- #(.cfg_p(cfg_p))
- perf
- (.clk_i(clk_i)
- ,.reset_i(reset_i)
-
- ,.mhartid_i(be_calculator.proc_cfg.core_id)
-
- ,.fe_nop_i(be_calculator.exc_stage_r[2].fe_nop_v)
- ,.be_nop_i(be_calculator.exc_stage_r[2].be_nop_v)
- ,.me_nop_i(be_calculator.exc_stage_r[2].me_nop_v)
- ,.poison_i(be_calculator.exc_stage_r[2].poison_v)
- ,.roll_i(be_calculator.exc_stage_r[2].roll_v)
- ,.instr_cmt_i(be_calculator.calc_status.mem3_cmt_v)
-
- ,.program_finish_i(testbench.program_finish)
- );
-*/
-/*if (dram_trace_p)
- bp_mem_nonsynth_tracer
- #(.cfg_p(cfg_p))
- bp_mem_tracer
- (.clk_i(clk_i & (testbench.dram_trace_p == 1))
- ,.reset_i(reset_i)
-
- ,.mem_cmd_i(dram_cmd_li)
- ,.mem_cmd_v_i(dram_cmd_v_li)
- ,.mem_cmd_yumi_i(dram_cmd_yumi_lo)
-
- ,.mem_resp_i(dram_resp_lo)
- ,.mem_resp_v_i(dram_resp_v_lo)
- ,.mem_resp_ready_i(dram_resp_ready_li)
- );
-
-if (cce_trace_p)
- bind bp_cce_top
- bp_cce_nonsynth_tracer
- #(.cfg_p(cfg_p))
- bp_cce_tracer
- (.clk_i(clk_i & (testbench.cce_trace_p == 1))
- ,.reset_i(reset_i)
-
- ,.cce_id_i(cce_id_i)
-
- // To CCE
- ,.lce_req_i(lce_req_to_cce)
- ,.lce_req_v_i(lce_req_v_to_cce)
- ,.lce_req_yumi_i(lce_req_yumi_from_cce)
- ,.lce_resp_i(lce_resp_to_cce)
- ,.lce_resp_v_i(lce_resp_v_to_cce)
- ,.lce_resp_yumi_i(lce_resp_yumi_from_cce)
-
- // From CCE
- ,.lce_cmd_i(lce_cmd_o)
- ,.lce_cmd_v_i(lce_cmd_v_o)
- ,.lce_cmd_ready_i(lce_cmd_ready_i)
-
- // To CCE
- ,.mem_resp_i(mem_resp_to_cce)
- ,.mem_resp_v_i(mem_resp_v_to_cce)
- ,.mem_resp_yumi_i(mem_resp_yumi_from_cce)
-
- // From CCE
- ,.mem_cmd_i(mem_cmd_from_cce)
- ,.mem_cmd_v_i(mem_cmd_v_from_cce)
- ,.mem_cmd_ready_i(mem_cmd_ready_to_cce)
- );
-*/
-// DRAM + link
-bp_me_cce_to_wormhole_link_client
- #(.cfg_p(cfg_p))
- client_link
- (.clk_i(clk_i)
- ,.reset_i(reset_i)
-
- ,.mem_cmd_o(mem_cmd_lo)
- ,.mem_cmd_v_o(mem_cmd_v_lo)
- ,.mem_cmd_yumi_i(mem_cmd_yumi_li)
-
- ,.mem_resp_i(mem_resp_li)
- ,.mem_resp_v_i(mem_resp_v_li)
- ,.mem_resp_ready_o(mem_resp_ready_lo)
-
- ,.my_cord_i(dram_cord_lo)
- ,.my_cid_i(mem_noc_cid_width_p'(0))
-
- ,.cmd_link_i(mem_cmd_link_li)
- ,.cmd_link_o(mem_cmd_link_lo)
-
- ,.resp_link_i(mem_resp_link_li)
- ,.resp_link_o(mem_resp_link_lo)
- );
-
-bp2wb_convertor
- #(.cfg_p(cfg_p))
-bp2wb
- (.clk_i(clk_i)
- ,.reset_i(reset_i)
- ,.mem_cmd_i(dram_cmd_li)
- ,.mem_cmd_v_i(dram_cmd_v_li)
- ,.mem_cmd_yumi_o(dram_cmd_yumi_lo)
- ,.mem_resp_o(dram_resp_lo)
- ,.mem_resp_v_o(dram_resp_v_lo)
- ,.mem_resp_ready_i(dram_resp_ready_li)
- ,.dat_i(wbm_dat_i)
- ,.dat_o(wbm_dat_o)
- ,.ack_i(wbm_ack_i)
- ,.adr_o(wbm_adr_o)
- ,.stb_o(wbm_stb_o)
- ,.cyc_o(wbm_cyc_o)
- ,.sel_o(wbm_sel_o )
- ,.we_o(wbm_we_o)
- ,.cti_o(wbm_cti_o)
- ,.bte_o(wbm_bte_o )
- );
-
-logic [num_core_p-1:0] program_finish;
-
-bp_nonsynth_host
- #(.cfg_p(cfg_p))
- host_mmio
- (.clk_i(clk_i)
- ,.reset_i(reset_i)
-
- ,.mem_cmd_i(host_cmd_li)
- ,.mem_cmd_v_i(host_cmd_v_li)
- ,.mem_cmd_yumi_o(host_cmd_yumi_lo)
-
- ,.mem_resp_o(host_resp_lo)
- ,.mem_resp_v_o(host_resp_v_lo)
- ,.mem_resp_ready_i(host_resp_ready_li)
-
- ,.program_finish_o(program_finish)
- ,.all_finished_debug_o(all_finished_debug_o)
- ,.core_passed_debug(core_passed_debug)
- ,.core_failed_debug(core_failed_debug)
- );
-
-/*bp_nonsynth_if_verif
- #(.cfg_p(cfg_p))
- if_verif
- ();
-*/
-// MMIO arbitration
-// Should this be on its own I/O router?
-logic req_outstanding_r;
-bsg_dff_reset_en
- #(.width_p(1))
- req_outstanding_reg
- (.clk_i(clk_i)
- ,.reset_i(reset_i)
- ,.en_i(mem_cmd_yumi_li | mem_resp_v_li)
-
- ,.data_i(mem_cmd_yumi_li)
- ,.data_o(req_outstanding_r)
- );
-
-wire host_cmd_not_dram = mem_cmd_v_lo & (mem_cmd_lo.addr < 39'h00_4000_0000 );//dram_base_addr_gp
-
-assign host_cmd_li = mem_cmd_lo;
-assign host_cmd_v_li = mem_cmd_v_lo & host_cmd_not_dram & ~req_outstanding_r;
-assign dram_cmd_li = mem_cmd_lo;
-assign dram_cmd_v_li = mem_cmd_v_lo & ~host_cmd_not_dram & ~req_outstanding_r;
-assign mem_cmd_yumi_li = host_cmd_not_dram
- ? host_cmd_yumi_lo
- : dram_cmd_yumi_lo;
-
-assign mem_resp_li = host_resp_v_lo ? host_resp_lo : dram_resp_lo;
-assign mem_resp_v_li = host_resp_v_lo | dram_resp_v_lo;
-assign host_resp_ready_li = mem_resp_ready_lo;
-assign dram_resp_ready_li = mem_resp_ready_lo;
-
-// CFG loader + rom + link
-bp_me_cce_to_wormhole_link_master
- #(.cfg_p(cfg_p))
- master_link
- (.clk_i(clk_i)
- ,.reset_i(reset_i)
-
- ,.mem_cmd_i(cfg_cmd_lo)
- ,.mem_cmd_v_i(cfg_cmd_ready_li & cfg_cmd_v_lo)
- ,.mem_cmd_ready_o(cfg_cmd_ready_li)
-
- ,.mem_resp_o(cfg_resp_li)
- ,.mem_resp_v_o(cfg_resp_v_li)
- ,.mem_resp_yumi_i(cfg_resp_ready_lo & cfg_resp_v_li)
-
- ,.my_cord_i(dram_cord_lo)
- ,.my_cid_i(mem_noc_cid_width_p'(0))
- ,.dram_cord_i(dram_cord_lo)
- ,.mmio_cord_i(mmio_cord_lo)
- ,.host_cord_i(host_cord_lo)
-
- ,.cmd_link_i(cfg_cmd_link_li)
- ,.cmd_link_o(cfg_cmd_link_lo)
-
- ,.resp_link_i(cfg_resp_link_li)
- ,.resp_link_o(cfg_resp_link_lo)
- );
-
-localparam cce_instr_ram_addr_width_lp = `BSG_SAFE_CLOG2(num_cce_instr_ram_els_p);
-bp_cce_mmio_cfg_loader
- #(.cfg_p(cfg_p)
- ,.inst_width_p(`bp_cce_inst_width)
- ,.inst_ram_addr_width_p(cce_instr_ram_addr_width_lp)
- ,.inst_ram_els_p(num_cce_instr_ram_els_p)
- ,.skip_ram_init_p(skip_init_p)
- )
- cfg_loader
- (.clk_i(clk_i)
- ,.reset_i(reset_i)
-
- ,.mem_cmd_o(cfg_cmd_lo)
- ,.mem_cmd_v_o(cfg_cmd_v_lo)
- ,.mem_cmd_yumi_i(cfg_cmd_ready_li & cfg_cmd_v_lo)
-
- ,.mem_resp_i(cfg_resp_li)
- ,.mem_resp_v_i(cfg_resp_v_li)
- ,.mem_resp_ready_o(cfg_resp_ready_lo)
- );
-
-endmodule
-
import bp_common_aviary_pkg::*;
import bp_cce_pkg::*;
import bp_me_pkg::*;
- #(parameter bp_cfg_e cfg_p = e_bp_single_core_cfg
- `declare_bp_proc_params(cfg_p)
- `declare_bp_me_if_widths(paddr_width_p, cce_block_width_p, num_lce_p, lce_assoc_p)
+ #(parameter bp_params_e bp_params_p = e_bp_single_core_cfg
+ `declare_bp_proc_params(bp_params_p)
+ `declare_bp_me_if_widths(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p)
// , parameter [paddr_width_p-1:0] dram_offset_p = '0
, localparam num_block_words_lp = cce_block_width_p / 64
, localparam wbone_addr_lbound = 3 //`BSG_SAFE_CLOG2(wbone_data_width / mem_granularity) //dword granularity
, localparam total_datafetch_cycle_lp = cce_block_width_p / wbone_data_width
, localparam total_datafetch_cycle_width = `BSG_SAFE_CLOG2(total_datafetch_cycle_lp)
- , localparam cached_addr_base = 32'h4000_4000// 32'h5000_0000
+ , localparam cached_addr_base = 32'h7000_0000//6000_0000 //32'h4000_4000//
)
- (input clk_i
- ,(* mark_debug = "true" *) input reset_i
+ ( input clk_i
+ ,(* mark_debug = "true" *) input reset_i
- // BP side
- ,(* mark_debug = "true" *) input [cce_mem_msg_width_lp-1:0] mem_cmd_i
- ,(* mark_debug = "true" *) input mem_cmd_v_i
- ,(* mark_debug = "true" *) output mem_cmd_yumi_o
+ // BP side
+ ,(* mark_debug = "true" *) input [cce_mem_msg_width_lp-1:0] mem_cmd_i
+ ,(* mark_debug = "true" *) input mem_cmd_v_i
+ ,(* mark_debug = "true" *) output mem_cmd_ready_o
- , (* mark_debug = "true" *) output [cce_mem_msg_width_lp-1:0] mem_resp_o
+ , output [cce_mem_msg_width_lp-1:0] mem_resp_o
, (* mark_debug = "true" *) output mem_resp_v_o
- , (* mark_debug = "true" *) input mem_resp_ready_i
+ , (* mark_debug = "true" *) input mem_resp_yumi_i
// Wishbone side
, (* mark_debug = "true" *) input [63:0] dat_i
, (* mark_debug = "true" *) output logic [63:0] dat_o
, (* mark_debug = "true" *) input ack_i
- // , input err_i
- // , input rty_i
+ , input err_i
+// , input rty_i
, (* mark_debug = "true" *) output logic [wbone_addr_ubound-wbone_addr_lbound-1:0] adr_o//TODO: Double check!!!
, (* mark_debug = "true" *) output logic stb_o
, output cyc_o
- , output sel_o //TODO: double check!!!
+ , output [7:0] sel_o //TODO: double check!!!
, (* mark_debug = "true" *) output we_o
, output [2:0] cti_o //TODO: hardwire in Litex
, output [1:0] bte_o //TODO: hardwire in Litex
);
- `declare_bp_me_if(paddr_width_p, cce_block_width_p, num_lce_p, lce_assoc_p);
+ `declare_bp_me_if(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p);
//locals
(* mark_debug = "true" *) logic [total_datafetch_cycle_width:0] ack_ctr = 0;
- (* mark_debug = "true" *) bp_cce_mem_msg_s mem_cmd_cast_i, mem_resp_cast_o, mem_cmd_r;
+ (* mark_debug = "true" *) bp_cce_mem_msg_s mem_cmd_cast_i, mem_resp_cast_o, mem_cmd_debug;//, mem_cmd_debug2
(* mark_debug = "true" *) logic ready_li, v_li, stb_justgotack;
(* mark_debug = "true" *) logic [cce_block_width_p-1:0] data_lo;
(* mark_debug = "true" *) logic [cce_block_width_p-1:0] data_li;
(* mark_debug = "true" *) wire [paddr_width_p-1:0] mem_cmd_addr_l;
- (* mark_debug = "true" *) logic [paddr_width_p-1:0] addr_lo;
(* mark_debug = "true" *) logic set_stb;
- (* mark_debug = "true" *) wire [63:0] data_little_end;
- //reset
- //TODO: reset ack_ctr here
//Handshaking between Wishbone and BlackParrot through convertor
//3.1.3:At every rising edge of [CLK_I] the terminating signal(ACK) is sampled. If it
//is asserted, then [STB_O] is negated.
-
- assign ready_li = ( ack_ctr == 0 );
- assign mem_cmd_yumi_o = mem_cmd_v_i && ready_li;//!stb_o then ready to take!
+
+ assign ready_li = ( ack_ctr == 0 ) & !set_stb & !mem_resp_v_o;
+ assign mem_cmd_ready_o = ready_li;//!stb_o then ready to take!
// assign v_li = (ack_ctr == total_datafetch_cycle_lp-1);
- assign mem_resp_v_o = mem_resp_ready_i & v_li;
- assign stb_o = (set_stb) && !stb_justgotack; //addresi mem_cmd_rdan aldigimiz icin 1 cycle geriden geliyo
+ assign mem_resp_v_o = v_li;
+ assign stb_o = (set_stb) && !stb_justgotack;
assign cyc_o = stb_o;
- assign sel_o = 0;
+ assign sel_o = 8'b11111111;
assign cti_o = 0;
assign bte_o = 0;
initial begin
ack_ctr = 0;
- //stb_reset_lo =0;
end
-/* always_ff @(posedge clk_i)
- if ( mem_cmd_yumi_o )// || (ack_ctr > 0))
- begin
- data_li <= 0;
- set_stb <= 1;
- end
-*/
-
//Flip stb after each ack--->RULE 3.20:
-
// Every time we get an ACK from WB, increment counter until the counter reaches to total_datafetch_cycle_lp
-assign data_little_end = dat_i;
always_ff @(posedge clk_i)
begin
set_stb <= 0;
v_li <=0;
end
-
- else if (mem_cmd_yumi_o)
+ else if (v_li)
+ begin
+ if (mem_resp_yumi_i)
+ begin
+ v_li <= 0;
+ ack_ctr <= 0;
+ end
+ end
+ else if (mem_cmd_v_i)
begin
- data_li <= 0;
+ //data_li <= 0;
set_stb <= 1;
v_li <= 0;
stb_justgotack <= 0;
if (ack_i)//stb should be negated after ack
begin
stb_justgotack <= 1;
- data_li[(ack_ctr*wbone_data_width) +: wbone_data_width] <= data_little_end;
- if ((ack_ctr == total_datafetch_cycle_lp-1) || (mem_cmd_addr_l < cached_addr_base && mem_cmd_r.msg_type == e_cce_mem_uc_wr )) //if uncached store, just one cycle is fine
- begin
- ack_ctr <= 0;
+ data_li[(ack_ctr*wbone_data_width) +: wbone_data_width] <= dat_i;
+ if ((ack_ctr == total_datafetch_cycle_lp-1) || (mem_cmd_addr_l < cached_addr_base && mem_cmd_r.header.msg_type == e_cce_mem_uc_wr )) //if uncached store, just one cycle is fine
+ begin
v_li <=1;
set_stb <= 0;
end
end
//Packet Pass from BP to BP2WB
- assign mem_cmd_cast_i = mem_cmd_i;
-
- bsg_dff_reset_en
+ assign mem_cmd_cast_i = mem_cmd_i;
+ bp_cce_mem_msg_s mem_cmd_r;
+ bsg_dff_reset_en
#(.width_p(cce_mem_msg_width_lp))
mshr_reg
(.clk_i(clk_i)
,.reset_i(reset_i)
- ,.en_i(mem_cmd_yumi_o)//when
+ ,.en_i(mem_cmd_v_i)//when
,.data_i(mem_cmd_i)
,.data_o(mem_cmd_r)
);
-
//Addr && Data && Command Pass from BP2WB to WB
logic [wbone_addr_lbound-1:0] throw_away;
- assign mem_cmd_addr_l = mem_cmd_r.addr;
+ assign mem_cmd_addr_l = mem_cmd_r.header.addr;
assign data_lo = mem_cmd_r.data;
logic [39:0] mem_cmd_addr_l_zero64;
- logic [7:0] partial;
always_comb begin
if( mem_cmd_addr_l < cached_addr_base )
begin
else
begin
mem_cmd_addr_l_zero64 = mem_cmd_addr_l >> 6 << 6;
- // addr_lo =
{adr_o,throw_away} = mem_cmd_addr_l_zero64 + (ack_ctr*8);//TODO:careful
- // adr_o = addr_lo[wbone_addr_ubound-1:wbone_addr_lbound];
dat_o = data_lo[(ack_ctr*wbone_data_width) +: wbone_data_width];
- end
+ end
end
- assign we_o = (mem_cmd_r.msg_type inside {e_cce_mem_uc_wr, e_cce_mem_wb});
-
-//DEBUG
-
-wire [3:0] typean;
-assign typean = mem_cmd_r.msg_type;
-wire [2:0] debug1;
-assign debug1 = (mem_cmd_r.addr[5:0]>>3);
+ assign we_o = (mem_cmd_r.header.msg_type inside {e_cce_mem_uc_wr, e_cce_mem_wb});
//Data Pass from BP2WB to BP
-wire [cce_block_width_p-1:0] rd_word_offset = mem_cmd_r.addr[3+:3];
+wire [cce_block_width_p-1:0] rd_word_offset = mem_cmd_r.header.addr[3+:3];
//wire [cce_block_width_p-1:0] rd_byte_offset = mem_cmd_r.addr[0+:3];
wire [cce_block_width_p-1:0] rd_bit_shift = rd_word_offset*64; // We rely on receiver to adjust bits
-wire [cce_block_width_p-1:0] data_li_resp = (mem_cmd_r.msg_type == e_cce_mem_uc_rd)
+(* mark_debug = "true" *) wire [cce_block_width_p-1:0] data_li_resp = (mem_cmd_r.header.msg_type == e_cce_mem_uc_rd)
? data_li >> rd_bit_shift
: data_li;
+
+
assign mem_resp_cast_o = '{data : data_li_resp
- ,payload : mem_cmd_r.payload
- ,size : mem_cmd_r.size
- ,addr : mem_cmd_r.addr
- ,msg_type: mem_cmd_r.msg_type
+ ,header :'{payload : mem_cmd_r.header.payload
+ ,size : mem_cmd_r.header.size
+ ,addr : mem_cmd_r.header.addr
+ ,msg_type: mem_cmd_r.header.msg_type
+ }
};
assign mem_resp_o = mem_resp_cast_o;
+/*********************************************/
+/*DEBUG SECTION*/
+/* always_comb
+ begin
+ if (mem_cmd_yumi_o == 1)// && mem_cmd_addr_l >=32'h8000_0000)
+ begin
+ mem_cmd_debug = mem_cmd_i;
+ if(mem_cmd_debug.addr >= 32'h80000000)
+ begin
+ $display("myarray == %x", mem_cmd_debug.addr);
+ $display("myarray == %x", mem_cmd_debug.msg_type);
+ if(mem_cmd_debug.msg_type>=3)
+ $display("myarray == %x", mem_cmd_debug.data);
+
+ end
+ end
+ end
+
+always_comb
+begin
+ if(mem_resp_v_o)
+ begin
+ mem_cmd_debug2 = mem_resp_o;
+ if(mem_cmd_debug2.addr >= 32'h80000000)
+ begin
+ $display("myresp == %x", mem_cmd_debug2.addr);
+ $display("myresp == %x", mem_cmd_debug2.msg_type);
+ if(mem_cmd_debug2.msg_type<=1)
+ $display("myresp == %x", mem_cmd_debug2.data);
+ end
+ end
+end
+*/
+
+/*wire [3:0] fake_msg_type;
+wire [10:0] fake_payload;
+wire [2:0] fake_size;
+wire [39:0] fake_addr;
+assign fake_payload = mem_cmd_r.header.payload;
+assign fake_size = mem_cmd_r.header.size;
+assign fake_addr = mem_cmd_r.header.addr;
+assign fake_msg_type = mem_cmd_r.header.msg_type;
+*/
+(* mark_debug = "true" *) logic debug_wire;
+ initial begin
+ debug_wire = 0;
+ end
+
+ assign mem_cmd_debug = mem_cmd_i;
+
+always_ff @(posedge clk_i)
+debug_wire <= (ack_i && mem_cmd_debug.header.addr >= 32'h80000000);
+
+/* always_ff @(posedge clk_i)
+ begin
+ if(mem_cmd_v_i && mem_cmd_debug.header.addr >= 32'h80000000)
+ begin
+ debug_wire <= 1;
+ // $display("addr == %x", mem_cmd_debug.header.addr);
+ end*/
+/* if (mem_resp_v_o && debug_ctr < 64 && mem_cmd_debug.header.addr >= 32'h80000000)
+ begin
+ debug_gotdata[((debug_ctr-1)*512) +: 512] <= data_li_resp;
+ $display("data == %x", data_li_resp);
+ end*/
+// end
+
+wire [3:0] typean;
+assign typean = mem_cmd_r.header.msg_type;
+
endmodule
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