fix sv_analysis.py for 3R-1W-CRo case, add fmadds/fmsubs and SVP64 tests

diff --git a/openpower/isatables/RM-1P-3S1D.csv b/openpower/isatables/RM-1P-3S1D.csv
index 9fbc3f0dff2c0a82c2b17346068b9693264b09ae..e61c76fb25d02986c0766226694c0fdc3d9d5fd7 100644 (file)
--- a/openpower/isatables/RM-1P-3S1D.csv
+++ b/openpower/isatables/RM-1P-3S1D.csv
@@ -31,3 +31,12 @@ isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
 isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
 isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
 isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
+fmsubs,1P,EXTRA2,d:FRT;d:CR1,s:FRA,s:FRB,s:FRC,FRA,FRB,FRC,FRT,0,CR1,0
+fmadds,1P,EXTRA2,d:FRT;d:CR1,s:FRA,s:FRB,s:FRC,FRA,FRB,FRC,FRT,0,CR1,0
+fnmsubs,1P,EXTRA2,d:FRT;d:CR1,s:FRA,s:FRB,s:FRC,FRA,FRB,FRC,FRT,0,CR1,0
+fnmadds,1P,EXTRA2,d:FRT;d:CR1,s:FRA,s:FRB,s:FRC,FRA,FRB,FRC,FRT,0,CR1,0
+fsel,1P,EXTRA2,d:FRT;d:CR1,s:FRA,s:FRB,s:FRC,FRA,FRB,FRC,FRT,0,CR1,0
+fmsub,1P,EXTRA2,d:FRT;d:CR1,s:FRA,s:FRB,s:FRC,FRA,FRB,FRC,FRT,0,CR1,0
+fmadd,1P,EXTRA2,d:FRT;d:CR1,s:FRA,s:FRB,s:FRC,FRA,FRB,FRC,FRT,0,CR1,0
+fnmsub,1P,EXTRA2,d:FRT;d:CR1,s:FRA,s:FRB,s:FRC,FRA,FRB,FRC,FRT,0,CR1,0
+fnmadd,1P,EXTRA2,d:FRT;d:CR1,s:FRA,s:FRB,s:FRC,FRA,FRB,FRC,FRT,0,CR1,0

diff --git a/src/openpower/decoder/isa/test_caller_svp64_fp.py b/src/openpower/decoder/isa/test_caller_svp64_fp.py
index 3ba7fd8efa80786958c6cd4f0394788757aa499e..830d472ed63c2e95e7b07adae7f0ee4628f995f8 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64_fp.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_fp.py
@@ -131,7 +131,6 @@ class DecoderTestCase(FHDLTestCase):
             self.assertEqual(sim.fpr(3), SelectableInt(0x4040266660000000, 64))
             self.assertEqual(sim.fpr(4), SelectableInt(0xC004000000000000, 64))
 
-
     def test_sv_fpadd(self):
         """>>> lst = ["sv.fadds 6.v, 2.v, 4.v"
                         ]
@@ -158,6 +157,38 @@ class DecoderTestCase(FHDLTestCase):
             self.assertEqual(sim.fpr(6), SelectableInt(0x0, 64))
             self.assertEqual(sim.fpr(7), SelectableInt(0xc050266660000000, 64))
 
+    def test_sv_fpmadds(self):
+        """>>> lst = ["sv.fmadds 6.v, 2.v, 4.v, 8"
+                        ]
+            two vector mul-adds with a scalar in f8
+            * fp6 = fp2 * fp4 + f8 = 7.0 * 2.0 - 2.0 = 12.0
+            * fp7 = fp3 * fp5 + f8 = 7.0 * 2.0 - 2.0 = 12.0
+        """
+        lst = SVP64Asm(["sv.fmadds 6.v, 2.v, 4.v, 8"
+                        ])
+        lst = list(lst)
+
+        fprs = [0] * 32
+        fprs[2] = 0x401C000000000000  # 7.0
+        fprs[3] = 0xC02399999999999A  # -9.8
+        fprs[4] = 0x4000000000000000  # 2.0
+        fprs[5] = 0xC040266660000000 # -32.3
+        fprs[6] = 0x4000000000000000  # 2.0
+        fprs[7] = 0x4000000000000000  # 2.0
+        fprs[8] = 0xc000000000000000  # -2.0
+
+        # SVSTATE (in this case, VL=2)
+        svstate = SVP64State()
+        svstate.vl[0:7] = 2 # VL
+        svstate.maxvl[0:7] = 2 # MAXVL
+        print ("SVSTATE", bin(svstate.spr.asint()))
+
+        with Program(lst, bigendian=False) as program:
+            sim = self.run_tst_program(program, svstate=svstate,
+                                       initial_fprs=fprs)
+            self.assertEqual(sim.fpr(6), SelectableInt(0x4028000000000000, 64))
+            self.assertEqual(sim.fpr(7), SelectableInt(0x4073a8a3c0000000, 64))
+
     def run_tst_program(self, prog, initial_regs=None,
                               svstate=None,
                               initial_mem=None,

diff --git a/src/openpower/decoder/isa/test_caller_svp64_mapreduce.py b/src/openpower/decoder/isa/test_caller_svp64_mapreduce.py
index 7a74edb3c87f9ceef1557c9a4c4c2cf47336772b..d592091966ca0eb4ec47bcf2fc56b909bbfc63ce 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64_mapreduce.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_mapreduce.py
@@ -95,6 +95,32 @@ class DecoderTestCase(FHDLTestCase):
             self.assertEqual(sim.fpr(3), SelectableInt(0xC02399999999999A, 64))
             self.assertEqual(sim.fpr(4), SelectableInt(0x4000000000000000, 64))
 
+    def test_sv_fpmadds(self):
+        """>>> lst = ["sv.fmadds/mr 6, 2.v, 4.v, 6"
+                        ]
+                this example uses f6 as a multiply-accumulate-sum mapreduce
+        """
+        lst = SVP64Asm(["sv.fmadds/mr 6, 2.v, 4.v, 6"
+                        ])
+        lst = list(lst)
+
+        fprs = [0] * 32
+        fprs[2] = 0x401C000000000000  # 7.0
+        fprs[3] = 0xC02399999999999A  # -9.8
+        fprs[4] = 0x4000000000000000  # 2.0
+        fprs[5] = 0xC040266660000000 # -32.3
+        fprs[6] = 0x4000000000000000  # 2.0
+
+        # SVSTATE (in this case, VL=2)
+        svstate = SVP64State()
+        svstate.vl[0:7] = 2 # VL
+        svstate.maxvl[0:7] = 2 # MAXVL
+        print ("SVSTATE", bin(svstate.spr.asint()))
+
+        with Program(lst, bigendian=False) as program:
+            sim = self.run_tst_program(program, svstate=svstate,
+                                       initial_fprs=fprs)
+            self.assertEqual(sim.fpr(6), SelectableInt(0x4074c8a3c0000000, 64))
 
     def run_tst_program(self, prog, initial_regs=None, svstate=None,
                               initial_mem=None,

diff --git a/src/openpower/sv/sv_analysis.py b/src/openpower/sv/sv_analysis.py
index a55d6f0ddc86142e338340728862fd3641fc6e25..e8cf258c36445ff996d0b2450b29488b77b5a327 100644 (file)
--- a/src/openpower/sv/sv_analysis.py
+++ b/src/openpower/sv/sv_analysis.py
@@ -229,7 +229,7 @@ def process_csvs():
     primarykeys.sort()
 
     # mapping to old SVPrefix "Forms"
-    mapsto = {'3R-1W-CRio': 'RM-1P-3S1D',
+    mapsto = {'3R-1W-CRo': 'RM-1P-3S1D',
               '2R-1W-CRio': 'RM-1P-2S1D',
               '2R-1W-CRi': 'RM-1P-3S1D',
               '2R-1W-CRo': 'RM-1P-2S1D',