count_bit: process(clk)
begin
if rising_edge(clk) then
- if start_cmd = '1' then
- bit_count <= cmd_clks_i;
- elsif state /= DATA then
- bit_count <= (others => '1');
- elsif sck_recv = '1' then
- bit_count <= std_ulogic_vector(unsigned(bit_count) - 1);
+ if rst = '1' then
+ bit_count <= (others => '0');
+ else
+ if start_cmd = '1' then
+ bit_count <= cmd_clks_i;
+ elsif state /= DATA then
+ bit_count <= (others => '1');
+ elsif sck_recv = '1' then
+ bit_count <= std_ulogic_vector(unsigned(bit_count) - 1);
+ end if;
end if;
end if;
end process;