/* All VM address space holes will implicitly start aligned to the
* size alignment, so we don't need to sanitize the alignment here
*/
- size = align(size, rws->size_align);
+ size = align(size, rws->info.gart_page_size);
pipe_mutex_lock(rws->bo_va_mutex);
/* first look for a hole */
{
struct radeon_bo_va_hole *hole;
- size = align(size, rws->size_align);
+ size = align(size, rws->info.gart_page_size);
pipe_mutex_lock(rws->bo_va_mutex);
if ((va + size) == rws->va_offset) {
pipe_mutex_destroy(bo->map_mutex);
if (bo->initial_domain & RADEON_DOMAIN_VRAM)
- rws->allocated_vram -= align(bo->base.size, rws->size_align);
+ rws->allocated_vram -= align(bo->base.size, rws->info.gart_page_size);
else if (bo->initial_domain & RADEON_DOMAIN_GTT)
- rws->allocated_gtt -= align(bo->base.size, rws->size_align);
+ rws->allocated_gtt -= align(bo->base.size, rws->info.gart_page_size);
FREE(bo);
}
}
if (initial_domains & RADEON_DOMAIN_VRAM)
- rws->allocated_vram += align(size, rws->size_align);
+ rws->allocated_vram += align(size, rws->info.gart_page_size);
else if (initial_domains & RADEON_DOMAIN_GTT)
- rws->allocated_gtt += align(size, rws->size_align);
+ rws->allocated_gtt += align(size, rws->info.gart_page_size);
return bo;
}
* BOs. Aligning this here helps the cached bufmgr. Especially small BOs,
* like constant/uniform buffers, can benefit from better and more reuse.
*/
- size = align(size, ws->size_align);
+ size = align(size, ws->info.gart_page_size);
/* Only set one usage bit each for domains and flags, or the cache manager
* might consider different sets of domains / flags compatible
pipe_mutex_unlock(ws->bo_handles_mutex);
}
- ws->allocated_gtt += align(bo->base.size, ws->size_align);
+ ws->allocated_gtt += align(bo->base.size, ws->info.gart_page_size);
return (struct pb_buffer*)bo;
}
bo->initial_domain = radeon_bo_get_initial_domain((void*)bo);
if (bo->initial_domain & RADEON_DOMAIN_VRAM)
- ws->allocated_vram += align(bo->base.size, ws->size_align);
+ ws->allocated_vram += align(bo->base.size, ws->info.gart_page_size);
else if (bo->initial_domain & RADEON_DOMAIN_GTT)
- ws->allocated_gtt += align(bo->base.size, ws->size_align);
+ ws->allocated_gtt += align(bo->base.size, ws->info.gart_page_size);
return (struct pb_buffer*)bo;