Add some flags for the upcoming checker.

arch/alpha/isa/decoder.isa:
    Mark store conditionals as serializing.  This is slightly higher over head than they truly have in the 264, but it's close.  Normally they block any other instructions from entering the IQ until the IQ is empty.  This is higher overhead because it waits until the ROB is empty.

    Also mark RPCC as unverifiable.  The checker will just grab the value from the instruction and assume it's correct.
cpu/static_inst.hh:
    Add unverifiable flag, specifically for the CheckerCPU.

--HG--
extra : convert_revision : cbc34d1f2f5b07105d31d4bd8f19edae2cf8158e

diff --git a/arch/alpha/isa/decoder.isa b/arch/alpha/isa/decoder.isa
index 905ace4e1e7f1ae0c87d70721401aed75976fe64..ac9f9fc4c5001d220a40b28173cba2469f25802f 100644 (file)
--- a/arch/alpha/isa/decoder.isa
+++ b/arch/alpha/isa/decoder.isa
@@ -73,7 +73,9 @@ decode OPCODE default Unknown::unknown() {
                         uint64_t tmp = write_result;
                         // see stq_c
                         Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
-                    }}, mem_flags = LOCKED, inst_flags = IsNonSpeculative);
+                    }}, mem_flags = LOCKED, inst_flags = [IsNonSpeculative,
+                                                          IsSerializing,
+                                                          IsSerializeAfter]);
         0x2f: stq_c({{ Mem.uq = Ra; }},
                     {{
                         uint64_t tmp = write_result;
@@ -85,7 +87,9 @@ decode OPCODE default Unknown::unknown() {
                         // mailbox access, and we don't update the
                         // result register at all.
                         Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
-                    }}, mem_flags = LOCKED, inst_flags = IsNonSpeculative);
+                    }}, mem_flags = LOCKED, inst_flags = [IsNonSpeculative,
+                                                          IsSerializing,
+                                                          IsSerializeAfter]);
     }
 
     format IntegerOperate {
@@ -623,7 +627,7 @@ decode OPCODE default Unknown::unknown() {
 #else
                 Ra = curTick;
 #endif
-            }}, IsNonSpeculative);
+            }}, IsUnverifiable);
 
             // All of the barrier instructions below do nothing in
             // their execute() methods (hence the empty code blocks).

diff --git a/cpu/static_inst.hh b/cpu/static_inst.hh
index 550609ed76ea41d72cd1a51ddcce23747f4b0638..0b8fe2f18333bab37229359dced3b12ddc85f7c3 100644 (file)
--- a/cpu/static_inst.hh
+++ b/cpu/static_inst.hh
@@ -51,6 +51,7 @@ class AlphaDynInst;
 template <class Impl>
 class OzoneDynInst;
 
+class CheckerCPU;
 class FastCPU;
 class SimpleCPU;
 class InorderCPU;
@@ -128,6 +129,8 @@ class StaticInstBase : public RefCounted
         IsNonSpeculative, ///< Should not be executed speculatively
         IsQuiesce,
 
+        IsUnverifiable,
+
         NumFlags
     };
 
@@ -215,6 +218,7 @@ class StaticInstBase : public RefCounted
     bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
     bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
     bool isQuiesce() const { return flags[IsQuiesce]; }
+    bool isUnverifiable() const { return flags[IsUnverifiable]; }
     //@}
 
     /// Operation class.  Used to select appropriate function unit in issue.