[simplify-rtx][2/2] Use constants from pool when simplifying binops

	* simplify-rtx.c (simplify_binary_operation): If either operand was
	a constant pool reference use them if all other simplifications failed.

	* gcc.target/aarch64/fmul_fcvt_1.c: Add multiply-by-32 cases.

From-SVN: r229086

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 862b68b9ce682cb01a2af5ddbc6ae32f537735d6..e3398170ed4b910c02a6d38260c439f44a7a0b6a 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2015-10-20  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+       * simplify-rtx.c (simplify_binary_operation): If either operand was
+       a constant pool reference use them if all other simplifications failed.
+
 2015-10-20  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 
        * config/aarch64/aarch64.md

diff --git a/gcc/simplify-rtx.c b/gcc/simplify-rtx.c
index 1f91afc05213eb096e6cf5b768d2d3f9d7da5d8f..eb3f153485c5918d224b1a133cdcf7797c84f950 100644 (file)
--- a/gcc/simplify-rtx.c
+++ b/gcc/simplify-rtx.c
@@ -2001,7 +2001,17 @@ simplify_binary_operation (enum rtx_code code, machine_mode mode,
   tem = simplify_const_binary_operation (code, mode, trueop0, trueop1);
   if (tem)
     return tem;
-  return simplify_binary_operation_1 (code, mode, op0, op1, trueop0, trueop1);
+  tem = simplify_binary_operation_1 (code, mode, op0, op1, trueop0, trueop1);
+
+  if (tem)
+    return tem;
+
+  /* If the above steps did not result in a simplification and op0 or op1
+     were constant pool references, use the referenced constants directly.  */
+  if (trueop0 != op0 || trueop1 != op1)
+    return simplify_gen_binary (code, mode, trueop0, trueop1);
+
+  return NULL_RTX;
 }
 
 /* Subroutine of simplify_binary_operation.  Simplify a binary operation

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index d32bf0c0df7c4e4eb9b81eec7c66fdda2ef48850..2b6118fd8a35349b32f9f6b628fb597bc4ebe061 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2015-10-20  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+       * gcc.target/aarch64/fmul_fcvt_1.c: Add multiply-by-32 cases.
+
 2015-10-20  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 
        * gcc.target/aarch64/fmul_fcvt_1.c: New test.

diff --git a/gcc/testsuite/gcc.target/aarch64/fmul_fcvt_1.c b/gcc/testsuite/gcc.target/aarch64/fmul_fcvt_1.c
index 4e3ace79b5673477771d48ffa21bd94a0b631599..05e06e3729e59a73018ed647057ea42d9c9aa952 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/fmul_fcvt_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/fmul_fcvt_1.c
@@ -83,6 +83,16 @@ FUNC_DEFD (16)
 /* { dg-final { scan-assembler-times "fcvtzu\tx\[0-9\], d\[0-9\]*.*#4" 1 } } */
 /* { dg-final { scan-assembler-times "fcvtzu\tw\[0-9\], d\[0-9\]*.*#4" 1 } } */
 
+FUNC_DEFS (32)
+FUNC_DEFD (32)
+/* { dg-final { scan-assembler-times "fcvtzs\tw\[0-9\], s\[0-9\]*.*#5" 1 } } */
+/* { dg-final { scan-assembler-times "fcvtzs\tx\[0-9\], s\[0-9\]*.*#5" 1 } } */
+/* { dg-final { scan-assembler-times "fcvtzs\tx\[0-9\], d\[0-9\]*.*#5" 1 } } */
+/* { dg-final { scan-assembler-times "fcvtzs\tw\[0-9\], d\[0-9\]*.*#5" 1 } } */
+/* { dg-final { scan-assembler-times "fcvtzu\tw\[0-9\], s\[0-9\]*.*#5" 1 } } */
+/* { dg-final { scan-assembler-times "fcvtzu\tx\[0-9\], s\[0-9\]*.*#5" 1 } } */
+/* { dg-final { scan-assembler-times "fcvtzu\tx\[0-9\], d\[0-9\]*.*#5" 1 } } */
+/* { dg-final { scan-assembler-times "fcvtzu\tw\[0-9\], d\[0-9\]*.*#5" 1 } } */
 
 #define FUNC_TESTS(__a, __b)                                   \
 do                                                             \
@@ -120,10 +130,12 @@ main (void)
       FUNC_TESTS (4, i);
       FUNC_TESTS (8, i);
       FUNC_TESTS (16, i);
+      FUNC_TESTS (32, i);
 
       FUNC_TESTD (4, i);
       FUNC_TESTD (8, i);
       FUNC_TESTD (16, i);
+      FUNC_TESTD (32, i);
     }
   return 0;
 }