Remove mem parameter. Now the translating port asks the CPU's dcache's peer for...

configs/example/fs.py:
configs/example/se.py:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/cpu/simple/timing.cc:
src/cpu/simple_thread.cc:
src/cpu/simple_thread.hh:
src/cpu/thread_state.cc:
src/cpu/thread_state.hh:
tests/configs/o3-timing-mp.py:
tests/configs/o3-timing.py:
tests/configs/simple-atomic-mp.py:
tests/configs/simple-atomic.py:
tests/configs/simple-timing-mp.py:
tests/configs/simple-timing.py:
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-atomic.py:
tests/configs/tsunami-simple-timing-dual.py:
tests/configs/tsunami-simple-timing.py:
    No need for mem parameter any more.
src/cpu/checker/cpu.cc:
    Use new constructor for simple thread (no more MemObject parameter).
src/cpu/checker/cpu.hh:
    Remove MemObject parameter.
src/cpu/memtest/memtest.hh:
    Ports now take in their MemObject owner.
src/cpu/o3/alpha/cpu_builder.cc:
    Remove mem parameter.
src/cpu/o3/alpha/cpu_impl.hh:
    Remove memory parameter and clean up handling of TranslatingPort.
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/mips/cpu_builder.cc:
src/cpu/o3/mips/cpu_impl.hh:
src/cpu/o3/params.hh:
src/cpu/o3/thread_state.hh:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_builder.cc:
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/ozone/simple_params.hh:
src/cpu/ozone/thread_state.hh:
src/cpu/simple/atomic.cc:
    Remove memory parameter.

--HG--
extra : convert_revision : 43cb44a33b31320d44b69679dcf646c0380d07d3

diff --git a/configs/example/fs.py b/configs/example/fs.py
index 76b62a066b2b67d45afd11fb615b66095c52d1dd..26089aa16d7593ae146167518e4994c111959fc2 100644 (file)
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -137,13 +137,11 @@ for i in xrange(np):
         test_sys.cpu[i].addPrivateSplitL1Caches(MyCache(size = '32kB'),
                                                   MyCache(size = '64kB'))
     test_sys.cpu[i].connectMemPorts(test_sys.membus)
-    test_sys.cpu[i].mem = test_sys.physmem
 
 if len(bm) == 2:
     drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
     drive_sys.cpu = DriveCPUClass(cpu_id=0)
     drive_sys.cpu.connectMemPorts(drive_sys.membus)
-    drive_sys.cpu.mem = drive_sys.physmem
     root = makeDualRoot(test_sys, drive_sys, options.etherdump)
 elif len(bm) == 1:
     root = Root(clock = '1THz', system = test_sys)
@@ -163,8 +161,6 @@ if options.standard_switch:
             switch_cpus[i].addPrivateSplitL1Caches(MyCache(size = '32kB'),
                                                     MyCache(size = '64kB'))
 
-        switch_cpus[i].mem = test_sys.physmem
-        switch_cpus1[i].mem = test_sys.physmem
         switch_cpus[i].connectMemPorts(test_sys.membus)
         root.switch_cpus = switch_cpus
         root.switch_cpus1 = switch_cpus1

diff --git a/configs/example/se.py b/configs/example/se.py
index 2e63e27da36c06d70a3a5411dcb1df925477f68b..7261aeb3470d9c3ca778a67dc23c8fc609d63406 100644 (file)
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -39,7 +39,7 @@ parser = optparse.OptionParser()
 
 # Benchmark options
 parser.add_option("-c", "--cmd",
-                  default="../../tests/test-progs/hello/bin/alpha/linux/hello",
+                  default="../tests/test-progs/hello/bin/alpha/linux/hello",
                   help="The binary to run in syscall emulation mode.")
 parser.add_option("-o", "--options", default="",
                   help="The options to pass to the binary, use \" \" around the entire\
@@ -131,7 +131,6 @@ system = System(cpu = cpu,
                 membus = Bus())
 system.physmem.port = system.membus.port
 system.cpu.connectMemPorts(system.membus)
-system.cpu.mem = system.physmem
 system.cpu.clock = '2GHz'
 if options.caches and not options.standard_switch:
     system.cpu.addPrivateSplitL1Caches(MyCache(size = '32kB'),
@@ -155,8 +154,6 @@ if options.standard_switch:
 
     switch_cpu.workload = process
     switch_cpu1.workload = process
-    switch_cpu.mem = system.physmem
-    switch_cpu1.mem = system.physmem
     switch_cpu.connectMemPorts(system.membus)
     root.switch_cpu = switch_cpu
     root.switch_cpu1 = switch_cpu1

diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc
index 9cb6b032e49dd76f6282479f303f92856dd737f8..2e81b7b31a9ac0fa03b7a63ca5a0b51fca7a76e2 100644 (file)
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu.cc
@@ -72,6 +72,12 @@ CheckerCPU::CheckerCPU(Params *p)
     systemPtr = NULL;
 #else
     process = p->process;
+    thread = new SimpleThread(this, /* thread_num */ 0, process,
+                              /* asid */ 0);
+
+    thread->setStatus(ThreadContext::Suspended);
+    tc = thread->getTC();
+    threadContexts.push_back(tc);
 #endif
 
     result.integer = 0;
@@ -81,20 +87,6 @@ CheckerCPU::~CheckerCPU()
 {
 }
 
-void
-CheckerCPU::setMemory(MemObject *mem)
-{
-#if !FULL_SYSTEM
-    memPtr = mem;
-    thread = new SimpleThread(this, /* thread_num */ 0, process,
-                              /* asid */ 0, mem);
-
-    thread->setStatus(ThreadContext::Suspended);
-    tc = thread->getTC();
-    threadContexts.push_back(tc);
-#endif
-}
-
 void
 CheckerCPU::setSystem(System *system)
 {

diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 00b01171f46514aa3714eb90adb59b839418cee0..336cb1714b72eb2e7dcbff452336d6011b9c4a2c 100644 (file)
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -112,10 +112,6 @@ class CheckerCPU : public BaseCPU
 
     Process *process;
 
-    void setMemory(MemObject *mem);
-
-    MemObject *memPtr;
-
     void setSystem(System *system);
 
     System *systemPtr;

diff --git a/src/cpu/memtest/memtest.hh b/src/cpu/memtest/memtest.hh
index edde4a3b29a3e70f8bb29cd81ef048c29baf0ea3..2694efd39d00ae92aa54811972dd7decb376515f 100644 (file)
--- a/src/cpu/memtest/memtest.hh
+++ b/src/cpu/memtest/memtest.hh
@@ -97,7 +97,7 @@ class MemTest : public MemObject
       public:
 
         CpuPort(const std::string &_name, MemTest *_memtest)
-            : Port(_name), memtest(_memtest)
+            : Port(_name, _memtest), memtest(_memtest)
         { }
 
       protected:

diff --git a/src/cpu/o3/alpha/cpu_builder.cc b/src/cpu/o3/alpha/cpu_builder.cc
index ff123a6f7b2e2e5b118f71b04869d70c73c17a68..ca316433bc04e853359af59e349c7f43f827568e 100644 (file)
--- a/src/cpu/o3/alpha/cpu_builder.cc
+++ b/src/cpu/o3/alpha/cpu_builder.cc
@@ -61,8 +61,6 @@ Param<Tick> profile;
 SimObjectVectorParam<Process *> workload;
 #endif // FULL_SYSTEM
 
-SimObjectParam<MemObject *> mem;
-
 SimObjectParam<BaseCPU *> checker;
 
 Param<Counter> max_insts_any_thread;
@@ -169,8 +167,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivO3CPU)
     INIT_PARAM(workload, "Processes to run"),
 #endif // FULL_SYSTEM
 
-    INIT_PARAM(mem, "Memory"),
-
     INIT_PARAM_DFLT(checker, "Checker CPU", NULL),
 
     INIT_PARAM_DFLT(max_insts_any_thread,
@@ -314,8 +310,6 @@ CREATE_SIM_OBJECT(DerivO3CPU)
     params->workload = workload;
 #endif // FULL_SYSTEM
 
-    params->mem = mem;
-
     params->checker = checker;
 
     params->max_insts_any_thread = max_insts_any_thread;

diff --git a/src/cpu/o3/alpha/cpu_impl.hh b/src/cpu/o3/alpha/cpu_impl.hh
index b7362fad914fc53d371758b59f94fe10cd568b02..5deee27de951bcd6b3dbc9c8b32dc2c103489443 100644 (file)
--- a/src/cpu/o3/alpha/cpu_impl.hh
+++ b/src/cpu/o3/alpha/cpu_impl.hh
@@ -77,24 +77,10 @@ AlphaO3CPU<Impl>::AlphaO3CPU(Params *params)
         if (i < params->workload.size()) {
             DPRINTF(O3CPU, "Workload[%i] process is %#x",
                     i, this->thread[i]);
-            this->thread[i] = new Thread(this, i, params->workload[i],
-                                         i, params->mem);
+            this->thread[i] = new Thread(this, i, params->workload[i], i);
 
             this->thread[i]->setStatus(ThreadContext::Suspended);
 
-#if !FULL_SYSTEM
-            /* Use this port to for syscall emulation writes to memory. */
-            Port *mem_port;
-            TranslatingPort *trans_port;
-            trans_port = new TranslatingPort(csprintf("%s-%d-funcport",
-                                                      name(), i),
-                                             params->workload[i]->pTable,
-                                             false);
-            mem_port = params->mem->getPort("functional");
-            mem_port->setPeer(trans_port);
-            trans_port->setPeer(mem_port);
-            this->thread[i]->setMemPort(trans_port);
-#endif
             //usedTids[i] = true;
             //threadMap[i] = i;
         } else {
@@ -102,7 +88,7 @@ AlphaO3CPU<Impl>::AlphaO3CPU(Params *params)
             //when scheduling threads to CPU
             Process* dummy_proc = NULL;
 
-            this->thread[i] = new Thread(this, i, dummy_proc, i, params->mem);
+            this->thread[i] = new Thread(this, i, dummy_proc, i);
             //usedTids[i] = false;
         }
 #endif // !FULL_SYSTEM

diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 36750828852e3a1fb3a7d1aff3fe1296b6d47e94..dfe42d88223b53992ad249f9c6db9f8f625e4ed6 100644 (file)
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -187,7 +187,6 @@ FullO3CPU<Impl>::FullO3CPU(Params *params)
       system(params->system),
       physmem(system->physmem),
 #endif // FULL_SYSTEM
-      mem(params->mem),
       drainCount(0),
       deferRegistration(params->deferRegistration),
       numThreads(number_of_threads)
@@ -204,7 +203,6 @@ FullO3CPU<Impl>::FullO3CPU(Params *params)
 #if USE_CHECKER
         BaseCPU *temp_checker = params->checker;
         checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
-        checker->setMemory(mem);
 #if FULL_SYSTEM
         checker->setSystem(params->system);
 #endif

diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index fe510519cc7211c6d73affe14d020f716d00024b..2bf9cb23b6c37ed2feb22e14ef20fe32b14b8002 100644 (file)
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -620,9 +620,6 @@ class FullO3CPU : public BaseO3CPU
     PhysicalMemory *physmem;
 #endif
 
-    /** Pointer to memory. */
-    MemObject *mem;
-
     /** Event to call process() on once draining has completed. */
     Event *drainEvent;
 

diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index 5555bff85127e0227edde891c54b2a724649d9c9..cc9a8abf5567ceb41d7b5120cc1b6c74512f6b08 100644 (file)
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -329,8 +329,6 @@ class DefaultFetch
     /** Wire used to write any information heading to decode. */
     typename TimeBuffer<FetchStruct>::wire toDecode;
 
-    MemObject *mem;
-
     /** Icache interface. */
     IcachePort *icachePort;
 

diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index e7bf83b204da2a2c834b14deebb3ded46a7592f6..2b152e37650951cd0f769eaf83207ded3f584a94 100644 (file)
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -96,8 +96,7 @@ DefaultFetch<Impl>::IcachePort::recvRetry()
 
 template<class Impl>
 DefaultFetch<Impl>::DefaultFetch(Params *params)
-    : mem(params->mem),
-      branchPred(params),
+    : branchPred(params),
       decodeToFetchDelay(params->decodeToFetchDelay),
       renameToFetchDelay(params->renameToFetchDelay),
       iewToFetchDelay(params->iewToFetchDelay),

diff --git a/src/cpu/o3/mips/cpu_builder.cc b/src/cpu/o3/mips/cpu_builder.cc
index f1c3b33a5cbec0b89d94654b62df80a7dcebcdd8..ee9f2b48dc898acab16956e61d55044a1cb913ff 100644 (file)
--- a/src/cpu/o3/mips/cpu_builder.cc
+++ b/src/cpu/o3/mips/cpu_builder.cc
@@ -54,8 +54,6 @@ Param<int> activity;
 
 SimObjectVectorParam<Process *> workload;
 
-SimObjectParam<MemObject *> mem;
-
 SimObjectParam<BaseCPU *> checker;
 
 Param<Counter> max_insts_any_thread;
@@ -153,8 +151,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivO3CPU)
 
     INIT_PARAM(workload, "Processes to run"),
 
-    INIT_PARAM(mem, "Memory"),
-
     INIT_PARAM_DFLT(checker, "Checker CPU", NULL),
 
     INIT_PARAM_DFLT(max_insts_any_thread,
@@ -284,8 +280,6 @@ CREATE_SIM_OBJECT(DerivO3CPU)
 
     params->workload = workload;
 
-    params->mem = mem;
-
     params->checker = checker;
 
     params->max_insts_any_thread = max_insts_any_thread;

diff --git a/src/cpu/o3/mips/cpu_impl.hh b/src/cpu/o3/mips/cpu_impl.hh
index e087416264afafa739a611ea3229466b55ae21b4..97116fd3eac7f4df1ac73239b230b1df6e4ca86e 100644 (file)
--- a/src/cpu/o3/mips/cpu_impl.hh
+++ b/src/cpu/o3/mips/cpu_impl.hh
@@ -58,24 +58,10 @@ MipsO3CPU<Impl>::MipsO3CPU(Params *params)
         if (i < params->workload.size()) {
             DPRINTF(O3CPU, "Workload[%i] process is %#x",
                     i, this->thread[i]);
-            this->thread[i] = new Thread(this, i, params->workload[i],
-                                         i, params->mem);
+            this->thread[i] = new Thread(this, i, params->workload[i], i);
 
             this->thread[i]->setStatus(ThreadContext::Suspended);
 
-
-            /* Use this port to for syscall emulation writes to memory. */
-            Port *mem_port;
-            TranslatingPort *trans_port;
-            trans_port = new TranslatingPort(csprintf("%s-%d-funcport",
-                                                      name(), i),
-                                             params->workload[i]->pTable,
-                                             false);
-            mem_port = params->mem->getPort("functional");
-            mem_port->setPeer(trans_port);
-            trans_port->setPeer(mem_port);
-            this->thread[i]->setMemPort(trans_port);
-
             //usedTids[i] = true;
             //threadMap[i] = i;
         } else {
@@ -83,7 +69,7 @@ MipsO3CPU<Impl>::MipsO3CPU(Params *params)
             //when scheduling threads to CPU
             Process* dummy_proc = NULL;
 
-            this->thread[i] = new Thread(this, i, dummy_proc, i, params->mem);
+            this->thread[i] = new Thread(this, i, dummy_proc, i);
             //usedTids[i] = false;
         }
 

diff --git a/src/cpu/o3/params.hh b/src/cpu/o3/params.hh
index 1c234bcd762968e9859724ac628ec2e72cca493e..b487778c610d58ec9493163f8246163b6cece40f 100755 (executable)
--- a/src/cpu/o3/params.hh
+++ b/src/cpu/o3/params.hh
@@ -54,8 +54,6 @@ class O3Params : public BaseO3CPU::Params
     Process *process;
 #endif // FULL_SYSTEM
 
-    MemObject *mem;
-
     BaseCPU *checker;
 
     //

diff --git a/src/cpu/o3/thread_state.hh b/src/cpu/o3/thread_state.hh
index 5fe7bb94dbefc28d8fef284b23f009b180d5b5c8..d8720b3ab90a9f69d694daa374c862dfc7b85757 100644 (file)
--- a/src/cpu/o3/thread_state.hh
+++ b/src/cpu/o3/thread_state.hh
@@ -77,7 +77,7 @@ struct O3ThreadState : public ThreadState {
 
 #if FULL_SYSTEM
     O3ThreadState(O3CPU *_cpu, int _thread_num)
-        : ThreadState(-1, _thread_num),
+        : ThreadState(_cpu, -1, _thread_num),
           cpu(_cpu), inSyscall(0), trapPending(0)
     {
         if (cpu->params->profile) {
@@ -95,9 +95,8 @@ struct O3ThreadState : public ThreadState {
         profilePC = 3;
     }
 #else
-    O3ThreadState(O3CPU *_cpu, int _thread_num, Process *_process, int _asid,
-                  MemObject *mem)
-        : ThreadState(-1, _thread_num, _process, _asid, mem),
+    O3ThreadState(O3CPU *_cpu, int _thread_num, Process *_process, int _asid)
+        : ThreadState(_cpu, -1, _thread_num, _process, _asid),
           cpu(_cpu), inSyscall(0), trapPending(0)
     { }
 #endif

diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh
index 70ec1d101bce1d906e312147fe8be69c454729cc..28ff8e9bab6b68e20009b5d085713543d3635437 100644 (file)
--- a/src/cpu/ozone/cpu.hh
+++ b/src/cpu/ozone/cpu.hh
@@ -368,8 +368,6 @@ class OzoneCPU : public BaseCPU
 
     virtual Port *getPort(const std::string &name, int idx);
 
-    MemObject *mem;
-
     FrontEnd *frontEnd;
 
     BackEnd *backEnd;

diff --git a/src/cpu/ozone/cpu_builder.cc b/src/cpu/ozone/cpu_builder.cc
index 730158258f2f8bf82c0fd330fa7efaf5fc6056b4..39be9fd74eb589a0af662cd8614a6515faccc10d 100644 (file)
--- a/src/cpu/ozone/cpu_builder.cc
+++ b/src/cpu/ozone/cpu_builder.cc
@@ -69,8 +69,6 @@ SimObjectVectorParam<Process *> workload;
 //SimObjectParam<PageTable *> page_table;
 #endif // FULL_SYSTEM
 
-SimObjectParam<MemObject *> mem;
-
 SimObjectParam<BaseCPU *> checker;
 
 Param<Counter> max_insts_any_thread;
@@ -191,8 +189,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivOzoneCPU)
 //    INIT_PARAM(page_table, "Page table"),
 #endif // FULL_SYSTEM
 
-    INIT_PARAM_DFLT(mem, "Memory", NULL),
-
     INIT_PARAM_DFLT(checker, "Checker CPU", NULL),
 
     INIT_PARAM_DFLT(max_insts_any_thread,
@@ -350,7 +346,6 @@ CREATE_SIM_OBJECT(DerivOzoneCPU)
 //    params->pTable = page_table;
 #endif // FULL_SYSTEM
 
-    params->mem = mem;
     params->checker = checker;
     params->max_insts_any_thread = max_insts_any_thread;
     params->max_insts_all_threads = max_insts_all_threads;

diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh
index bf547bf943325770ccd49331cb70eb1bbb8d76f4..685bf3cb4aa55fdfc6b3390a96524e1a775d0107 100644 (file)
--- a/src/cpu/ozone/cpu_impl.hh
+++ b/src/cpu/ozone/cpu_impl.hh
@@ -93,10 +93,10 @@ OzoneCPU<Impl>::OzoneCPU(Params *p)
 #if FULL_SYSTEM
     : BaseCPU(p), thread(this, 0), tickEvent(this, p->width),
 #else
-    : BaseCPU(p), thread(this, 0, p->workload[0], 0, p->mem),
+    : BaseCPU(p), thread(this, 0, p->workload[0], 0),
       tickEvent(this, p->width),
 #endif
-      mem(p->mem), comm(5, 5)
+      comm(5, 5)
 {
     frontEnd = new FrontEnd(p);
     backEnd = new BackEnd(p);
@@ -107,7 +107,6 @@ OzoneCPU<Impl>::OzoneCPU(Params *p)
 #if USE_CHECKER
         BaseCPU *temp_checker = p->checker;
         checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
-        checker->setMemory(mem);
 #if FULL_SYSTEM
         checker->setSystem(p->system);
 #endif
@@ -198,19 +197,7 @@ OzoneCPU<Impl>::OzoneCPU(Params *p)
     frontEnd->renameTable.copyFrom(thread.renameTable);
     backEnd->renameTable.copyFrom(thread.renameTable);
 
-#if !FULL_SYSTEM
-    /* Use this port to for syscall emulation writes to memory. */
-    Port *mem_port;
-    TranslatingPort *trans_port;
-    trans_port = new TranslatingPort(csprintf("%s-%d-funcport",
-                                              name(), 0),
-                                     p->workload[0]->pTable,
-                                     false);
-    mem_port = p->mem->getPort("functional");
-    mem_port->setPeer(trans_port);
-    trans_port->setPeer(mem_port);
-    thread.setMemPort(trans_port);
-#else
+#if FULL_SYSTEM
     Port *mem_port;
     FunctionalPort *phys_port;
     VirtualPort *virt_port;

diff --git a/src/cpu/ozone/front_end.hh b/src/cpu/ozone/front_end.hh
index 2bdca35b950bfa3b083f73602e3952b290b36c71..e09e4de9c4a1dc7914b5d39679a8bf83c6f07c50 100644 (file)
--- a/src/cpu/ozone/front_end.hh
+++ b/src/cpu/ozone/front_end.hh
@@ -208,8 +208,6 @@ class FrontEnd
 
     IcachePort icachePort;
 
-    MemObject *mem;
-
     RequestPtr memReq;
 
     /** Mask to get a cache block's address. */

diff --git a/src/cpu/ozone/front_end_impl.hh b/src/cpu/ozone/front_end_impl.hh
index 36e87ec9c717fe5aa6524a46babb7d908efd67b7..b8fce42924a9a0696854adf64d4960a226e96adf 100644 (file)
--- a/src/cpu/ozone/front_end_impl.hh
+++ b/src/cpu/ozone/front_end_impl.hh
@@ -91,7 +91,6 @@ template <class Impl>
 FrontEnd<Impl>::FrontEnd(Params *params)
     : branchPred(params),
       icachePort(this),
-      mem(params->mem),
       numInstsReady(params->frontEndLatency, 0),
       instBufferSize(0),
       maxInstBufferSize(params->maxInstBufferSize),

diff --git a/src/cpu/ozone/lw_lsq.hh b/src/cpu/ozone/lw_lsq.hh
index dc58a8285795216aea6a7e8e6dd5ad485971595c..7e6849668afc5eab081262ddec7db10bf8533146 100644 (file)
--- a/src/cpu/ozone/lw_lsq.hh
+++ b/src/cpu/ozone/lw_lsq.hh
@@ -239,8 +239,6 @@ class OzoneLWLSQ {
     /** Pointer to the back-end stage. */
     BackEnd *be;
 
-    MemObject *mem;
-
     class DcachePort : public Port
     {
       protected:

diff --git a/src/cpu/ozone/lw_lsq_impl.hh b/src/cpu/ozone/lw_lsq_impl.hh
index 1f3f185028791e288d5cfbf502c965e5a261e042..ee1968626cb4275cfac3ae9e8cc03b3a377df27e 100644 (file)
--- a/src/cpu/ozone/lw_lsq_impl.hh
+++ b/src/cpu/ozone/lw_lsq_impl.hh
@@ -154,8 +154,6 @@ OzoneLWLSQ<Impl>::init(Params *params, unsigned maxLQEntries,
         SQIndices.push(i);
     }
 
-    mem = params->mem;
-
     usedPorts = 0;
     cachePorts = params->cachePorts;
 

diff --git a/src/cpu/ozone/simple_params.hh b/src/cpu/ozone/simple_params.hh
index 3f63d2e1dc4014427abe8ca1bbd9ad2e91712dc5..3e554c812d99c403a571e1adfe725a3edb6d02d2 100644 (file)
--- a/src/cpu/ozone/simple_params.hh
+++ b/src/cpu/ozone/simple_params.hh
@@ -61,8 +61,6 @@ class SimpleParams : public BaseCPU::Params
     //Page Table
     PageTable *pTable;
 
-    MemObject *mem;
-
     //
     // Caches
     //

diff --git a/src/cpu/ozone/thread_state.hh b/src/cpu/ozone/thread_state.hh
index c86f3552ec51ecf2fb2ccce737d184ac5a81d986..c226d7502eeb1eeee534aa57305dacccb7c73809 100644 (file)
--- a/src/cpu/ozone/thread_state.hh
+++ b/src/cpu/ozone/thread_state.hh
@@ -67,7 +67,7 @@ struct OzoneThreadState : public ThreadState {
 
 #if FULL_SYSTEM
     OzoneThreadState(CPUType *_cpu, int _thread_num)
-        : ThreadState(-1, _thread_num),
+        : ThreadState(_cpu, -1, _thread_num),
           intrflag(0), cpu(_cpu), inSyscall(0), trapPending(0)
     {
         if (cpu->params->profile) {
@@ -87,8 +87,8 @@ struct OzoneThreadState : public ThreadState {
     }
 #else
     OzoneThreadState(CPUType *_cpu, int _thread_num, Process *_process,
-                     int _asid, MemObject *mem)
-        : ThreadState(-1, _thread_num, _process, _asid, mem),
+                     int _asid)
+        : ThreadState(_cpu, -1, _thread_num, _process, _asid),
           cpu(_cpu), inSyscall(0), trapPending(0)
     {
         miscRegFile.clear();

diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index edba55b0da1a38b1270c04fea55abf7bdfa732e0..bfb80dc0fc40cedc5391a6b0c21692df6d3a96fb 100644 (file)
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -72,15 +72,6 @@ AtomicSimpleCPU::getPort(const std::string &if_name, int idx)
 void
 AtomicSimpleCPU::init()
 {
-    //Create Memory Ports (conect them up)
-//    Port *mem_dport = mem->getPort("");
-//    dcachePort.setPeer(mem_dport);
-//    mem_dport->setPeer(&dcachePort);
-
-//    Port *mem_iport = mem->getPort("");
-//    icachePort.setPeer(mem_iport);
-//    mem_iport->setPeer(&icachePort);
-
     BaseCPU::init();
 #if FULL_SYSTEM
     for (int i = 0; i < threadContexts.size(); ++i) {
@@ -500,7 +491,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
     Param<Counter> max_loads_any_thread;
     Param<Counter> max_loads_all_threads;
     Param<Tick> progress_interval;
-    SimObjectParam<MemObject *> mem;
     SimObjectParam<System *> system;
     Param<int> cpu_id;
 
@@ -533,7 +523,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
     INIT_PARAM(max_loads_all_threads,
                "terminate when all threads have reached this load count"),
     INIT_PARAM(progress_interval, "Progress interval"),
-    INIT_PARAM(mem, "memory"),
     INIT_PARAM(system, "system object"),
     INIT_PARAM(cpu_id, "processor ID"),
 
@@ -571,7 +560,6 @@ CREATE_SIM_OBJECT(AtomicSimpleCPU)
     params->functionTraceStart = function_trace_start;
     params->width = width;
     params->simulate_stalls = simulate_stalls;
-    params->mem = mem;
     params->system = system;
     params->cpu_id = cpu_id;
 

diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index cbb3980cbbf0c76e07969fe041153fd60be88f07..dc06c17f577aae5769ca4a3b554f1b7702dadb1b 100644 (file)
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -70,13 +70,13 @@ using namespace std;
 using namespace TheISA;
 
 BaseSimpleCPU::BaseSimpleCPU(Params *p)
-    : BaseCPU(p), mem(p->mem), thread(NULL)
+    : BaseCPU(p), thread(NULL)
 {
 #if FULL_SYSTEM
     thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb);
 #else
     thread = new SimpleThread(this, /* thread_num */ 0, p->process,
-            /* asid */ 0, mem);
+            /* asid */ 0);
 #endif // !FULL_SYSTEM
 
     thread->setStatus(ThreadContext::Suspended);

diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index af6b6f8352e7a08bbe60cc4d03b8ef947c36cfa4..f382158ddf1a39a15fa11386dc2e9e73572d9499 100644 (file)
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -76,8 +76,6 @@ class BaseSimpleCPU : public BaseCPU
     typedef TheISA::FloatReg FloatReg;
     typedef TheISA::FloatRegBits FloatRegBits;
 
-    MemObject *mem;
-
   protected:
     Trace::InstRecord *traceData;
 
@@ -95,7 +93,6 @@ class BaseSimpleCPU : public BaseCPU
   public:
     struct Params : public BaseCPU::Params
     {
-        MemObject *mem;
 #if FULL_SYSTEM
         AlphaITB *itb;
         AlphaDTB *dtb;

diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index fe6775ea4d158cf478e75be30c4092b296764e0d..9e1f091b538d3ee7f5fc2466d4959da747451fff 100644 (file)
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -660,7 +660,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU)
     Param<Counter> max_loads_any_thread;
     Param<Counter> max_loads_all_threads;
     Param<Tick> progress_interval;
-    SimObjectParam<MemObject *> mem;
     SimObjectParam<System *> system;
     Param<int> cpu_id;
 
@@ -693,7 +692,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU)
     INIT_PARAM(max_loads_all_threads,
                "terminate when all threads have reached this load count"),
     INIT_PARAM(progress_interval, "Progress interval"),
-    INIT_PARAM(mem, "memory"),
     INIT_PARAM(system, "system object"),
     INIT_PARAM(cpu_id, "processor ID"),
 
@@ -729,7 +727,6 @@ CREATE_SIM_OBJECT(TimingSimpleCPU)
     params->clock = clock;
     params->functionTrace = function_trace;
     params->functionTraceStart = function_trace_start;
-    params->mem = mem;
     params->system = system;
     params->cpu_id = cpu_id;
 

diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc
index 4fc47c982115651287ec15575835ef00b9769569..c89a13eef30445ff8529ccd2b5cb3f41839e12b1 100644 (file)
--- a/src/cpu/simple_thread.cc
+++ b/src/cpu/simple_thread.cc
@@ -62,7 +62,7 @@ using namespace std;
 SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
                            AlphaITB *_itb, AlphaDTB *_dtb,
                            bool use_kernel_stats)
-    : ThreadState(-1, _thread_num), cpu(_cpu), system(_sys), itb(_itb),
+    : ThreadState(_cpu, -1, _thread_num), cpu(_cpu), system(_sys), itb(_itb),
       dtb(_dtb)
 
 {
@@ -106,19 +106,10 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
 }
 #else
 SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num,
-                         Process *_process, int _asid, MemObject* memobj)
-    : ThreadState(-1, _thread_num, _process, _asid, memobj),
+                         Process *_process, int _asid)
+    : ThreadState(_cpu, -1, _thread_num, _process, _asid),
       cpu(_cpu)
 {
-    /* Use this port to for syscall emulation writes to memory. */
-    Port *mem_port;
-    port = new TranslatingPort(csprintf("%s-%d-funcport",
-                                        cpu->name(), tid),
-                               process->pTable, false);
-    mem_port = memobj->getPort("functional");
-    mem_port->setPeer(port);
-    port->setPeer(mem_port);
-
     regs.clear();
     tc = new ProxyThreadContext<SimpleThread>(this);
 }
@@ -127,9 +118,9 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num,
 
 SimpleThread::SimpleThread()
 #if FULL_SYSTEM
-    : ThreadState(-1, -1)
+    : ThreadState(NULL, -1, -1)
 #else
-    : ThreadState(-1, -1, NULL, -1, NULL)
+    : ThreadState(NULL, -1, -1, NULL, -1)
 #endif
 {
     tc = new ProxyThreadContext<SimpleThread>(this);
@@ -332,6 +323,25 @@ SimpleThread::delVirtPort(VirtualPort *vp)
     }
 }
 
+#else
+TranslatingPort *
+SimpleThread::getMemPort()
+{
+    if (port != NULL)
+        return port;
+
+    /* Use this port to for syscall emulation writes to memory. */
+    Port *dcache_port;
+    port = new TranslatingPort(csprintf("%s-%d-funcport",
+                                        cpu->name(), tid),
+                               process->pTable, false);
+    dcache_port = cpu->getPort("dcache_port");
+    assert(dcache_port != NULL);
+    dcache_port = dcache_port->getPeer();
+//    mem_port->setPeer(port);
+    port->setPeer(dcache_port);
+    return port;
+}
 
 #endif
 

diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index fe22e6c43d25c3a2a4a61d556f9dc4de30f45a8b..f002cbdceb33caa07f991d6306db796f66ae861c 100644 (file)
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -117,8 +117,7 @@ class SimpleThread : public ThreadState
                  AlphaITB *_itb, AlphaDTB *_dtb,
                  bool use_kernel_stats = true);
 #else
-    SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid,
-                 MemObject *memobj);
+    SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid);
 #endif
 
     SimpleThread();
@@ -174,6 +173,9 @@ class SimpleThread : public ThreadState
 
     bool simPalCheck(int palFunc);
 #else
+    // Override this function.
+    TranslatingPort *getMemPort();
+
     Fault translateInstReq(RequestPtr &req)
     {
         return process->pTable->translate(req);

diff --git a/src/cpu/thread_state.cc b/src/cpu/thread_state.cc
index c644ae8d75025d39900adfaadf729c19e92a6a7c..677ba65920d0404675b9d3a5847c9bd37efef3d3 100644 (file)
--- a/src/cpu/thread_state.cc
+++ b/src/cpu/thread_state.cc
@@ -29,8 +29,11 @@
  */
 
 #include "base/output.hh"
+#include "cpu/base.hh"
 #include "cpu/profile.hh"
 #include "cpu/thread_state.hh"
+#include "mem/port.hh"
+#include "mem/translating_port.hh"
 #include "sim/serialize.hh"
 
 #if FULL_SYSTEM
@@ -39,15 +42,16 @@
 #endif
 
 #if FULL_SYSTEM
-ThreadState::ThreadState(int _cpuId, int _tid)
-    : cpuId(_cpuId), tid(_tid), lastActivate(0), lastSuspend(0),
+ThreadState::ThreadState(BaseCPU *cpu, int _cpuId, int _tid)
+    : baseCpu(cpu), cpuId(_cpuId), tid(_tid), lastActivate(0), lastSuspend(0),
       profile(NULL), profileNode(NULL), profilePC(0), quiesceEvent(NULL),
+      physPort(NULL), virtPort(NULL),
       microPC(0), nextMicroPC(1), funcExeInst(0), storeCondFailures(0)
 #else
-ThreadState::ThreadState(int _cpuId, int _tid, Process *_process,
-                         short _asid, MemObject *mem)
-    : cpuId(_cpuId), tid(_tid), lastActivate(0), lastSuspend(0),
-      process(_process), asid(_asid),
+ThreadState::ThreadState(BaseCPU *cpu, int _cpuId, int _tid, Process *_process,
+                         short _asid)
+    : baseCpu(cpu), cpuId(_cpuId), tid(_tid), lastActivate(0), lastSuspend(0),
+      port(NULL), process(_process), asid(_asid),
       microPC(0), nextMicroPC(1), funcExeInst(0), storeCondFailures(0)
 #endif
 {
@@ -108,4 +112,31 @@ ThreadState::profileSample()
         profile->sample(profileNode, profilePC);
 }
 
+#else
+TranslatingPort *
+ThreadState::getMemPort()
+{
+    if (port != NULL)
+        return port;
+
+    /* Use this port to for syscall emulation writes to memory. */
+    Port *dcache_port, *func_mem_port;
+    port = new TranslatingPort(csprintf("%s-%d-funcport",
+                                        baseCpu->name(), tid),
+                               process->pTable, false);
+
+    dcache_port = baseCpu->getPort("dcache_port");
+    assert(dcache_port != NULL);
+
+    MemObject *mem_object = dcache_port->getPeer()->getOwner();
+    assert(mem_object != NULL);
+
+    func_mem_port = mem_object->getPort("functional");
+    assert(func_mem_port != NULL);
+
+    func_mem_port->setPeer(port);
+    port->setPeer(func_mem_port);
+
+    return port;
+}
 #endif

diff --git a/src/cpu/thread_state.hh b/src/cpu/thread_state.hh
index 60353760c5912a6923d86c4549b0d623a44d31f5..14673aabb8bf8852499c511d6aacbdd2c03d8639 100644 (file)
--- a/src/cpu/thread_state.hh
+++ b/src/cpu/thread_state.hh
@@ -37,7 +37,6 @@
 
 #if !FULL_SYSTEM
 #include "mem/mem_object.hh"
-#include "mem/translating_port.hh"
 #include "sim/process.hh"
 #endif
 
@@ -50,7 +49,9 @@ namespace Kernel {
 };
 #endif
 
+class BaseCPU;
 class Checkpoint;
+class TranslatingPort;
 
 /**
  *  Struct for holding general thread state that is needed across CPU
@@ -62,10 +63,10 @@ struct ThreadState {
     typedef ThreadContext::Status Status;
 
 #if FULL_SYSTEM
-    ThreadState(int _cpuId, int _tid);
+    ThreadState(BaseCPU *cpu, int _cpuId, int _tid);
 #else
-    ThreadState(int _cpuId, int _tid, Process *_process,
-                short _asid, MemObject *mem);
+    ThreadState(BaseCPU *cpu, int _cpuId, int _tid, Process *_process,
+                short _asid);
 #endif
 
     void serialize(std::ostream &os);
@@ -105,7 +106,7 @@ struct ThreadState {
 #else
     Process *getProcessPtr() { return process; }
 
-    TranslatingPort *getMemPort() { return port; }
+    TranslatingPort *getMemPort();
 
     void setMemPort(TranslatingPort *_port) { port = _port; }
 
@@ -153,6 +154,9 @@ struct ThreadState {
   protected:
     ThreadContext::Status _status;
 
+    // Pointer to the base CPU.
+    BaseCPU *baseCpu;
+
     // ID of this context w.r.t. the System or Process object to which
     // it belongs.  For full-system mode, this is the system CPU ID.
     int cpuId;

diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py
index 68631b3d251d816fbd0c5dd17b662eed491ce219..331e2c569dc34b88c679b8fde20450682e82a81c 100644 (file)
--- a/tests/configs/o3-timing-mp.py
+++ b/tests/configs/o3-timing-mp.py
@@ -71,7 +71,6 @@ system.l2c.mem_side = system.membus.port
 for cpu in cpus:
     cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
                                 L1(size = '32kB', assoc = 4))
-    cpu.mem = cpu.dcache
     # connect cpu level-1 caches to shared level-2 cache
     cpu.connectMemPorts(system.toL2Bus)
 

diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py
index 0dd7be5066721a2bf5f7004a7c9f7fd037f5f163..a66cd436e9a6a631bb5bf8fb1b52ba1524b5e99f 100644 (file)
--- a/tests/configs/o3-timing.py
+++ b/tests/configs/o3-timing.py
@@ -40,7 +40,6 @@ class MyCache(BaseCache):
 cpu = DerivO3CPU()
 cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
                               MyCache(size = '2MB'))
-cpu.mem = cpu.dcache
 
 system = System(cpu = cpu,
                 physmem = PhysicalMemory(),

diff --git a/tests/configs/simple-atomic-mp.py b/tests/configs/simple-atomic-mp.py
index eaa6ec66e42c15b67e72c69afd3b7aaa59627015..f9e4e27679bc168a59f2fc97a2bcdc561c63f626 100644 (file)
--- a/tests/configs/simple-atomic-mp.py
+++ b/tests/configs/simple-atomic-mp.py
@@ -70,7 +70,6 @@ system.l2c.mem_side = system.membus.port
 for cpu in cpus:
     cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
                                 L1(size = '32kB', assoc = 4))
-    cpu.mem = cpu.dcache
     # connect cpu level-1 caches to shared level-2 cache
     cpu.connectMemPorts(system.toL2Bus)
 

diff --git a/tests/configs/simple-atomic.py b/tests/configs/simple-atomic.py
index d35ac4ae0e9ec1e16ea90585bd2d7752e04a147d..a8a87699482820933c358fdab7283fadc146a497 100644 (file)
--- a/tests/configs/simple-atomic.py
+++ b/tests/configs/simple-atomic.py
@@ -34,6 +34,5 @@ system = System(cpu = AtomicSimpleCPU(cpu_id=0),
                 membus = Bus())
 system.physmem.port = system.membus.port
 system.cpu.connectMemPorts(system.membus)
-system.cpu.mem = system.physmem
 
 root = Root(system = system)

diff --git a/tests/configs/simple-timing-mp.py b/tests/configs/simple-timing-mp.py
index 8f9ab0dde367c52227b7fbe8f3349915c4f711a3..0d99d8714d9b4a9c05688329080558d15855af98 100644 (file)
--- a/tests/configs/simple-timing-mp.py
+++ b/tests/configs/simple-timing-mp.py
@@ -70,7 +70,6 @@ system.l2c.mem_side = system.membus.port
 for cpu in cpus:
     cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
                                 L1(size = '32kB', assoc = 4))
-    cpu.mem = cpu.dcache
     # connect cpu level-1 caches to shared level-2 cache
     cpu.connectMemPorts(system.toL2Bus)
 

diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py
index 60190b47c8bc28e38535e72ac103b3798555df79..d7d505a5ac2029ea19aab670c52d4b5966df1b71 100644 (file)
--- a/tests/configs/simple-timing.py
+++ b/tests/configs/simple-timing.py
@@ -39,8 +39,6 @@ class MyCache(BaseCache):
 cpu = TimingSimpleCPU(cpu_id=0)
 cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
                               MyCache(size = '2MB'))
-cpu.mem = cpu.dcache
-cpu.mem = cpu.dcache
 system = System(cpu = cpu,
                 physmem = PhysicalMemory(),
                 membus = Bus())

diff --git a/tests/configs/tsunami-simple-atomic-dual.py b/tests/configs/tsunami-simple-atomic-dual.py
index 1e6c10243603bb5c412dfcf3ce196aba7ee8d40e..4adb328684fc51e4bb6fecc73e791d71efcfffc3 100644 (file)
--- a/tests/configs/tsunami-simple-atomic-dual.py
+++ b/tests/configs/tsunami-simple-atomic-dual.py
@@ -36,6 +36,5 @@ system = FSConfig.makeLinuxAlphaSystem('atomic')
 system.cpu = cpus
 for c in cpus:
     c.connectMemPorts(system.membus)
-    c.mem = system.physmem
 
 root = Root(clock = '2GHz', system = system)

diff --git a/tests/configs/tsunami-simple-atomic.py b/tests/configs/tsunami-simple-atomic.py
index 623d285e4278f9c912852acae66acb76e562e815..653df9bb0d68174e420e56584bbea356130df77a 100644 (file)
--- a/tests/configs/tsunami-simple-atomic.py
+++ b/tests/configs/tsunami-simple-atomic.py
@@ -35,6 +35,5 @@ cpu = AtomicSimpleCPU(cpu_id=0)
 system = FSConfig.makeLinuxAlphaSystem('atomic')
 system.cpu = cpu
 cpu.connectMemPorts(system.membus)
-cpu.mem = system.physmem
 
 root = Root(clock = '2GHz', system = system)

diff --git a/tests/configs/tsunami-simple-timing-dual.py b/tests/configs/tsunami-simple-timing-dual.py
index 516495d18cb7d5964efc19cafee554036ebbee2b..bfd478969cfdcac72deb26698b5afdea84392abc 100644 (file)
--- a/tests/configs/tsunami-simple-timing-dual.py
+++ b/tests/configs/tsunami-simple-timing-dual.py
@@ -36,6 +36,5 @@ system = FSConfig.makeLinuxAlphaSystem('timing')
 system.cpu = cpus
 for c in cpus:
     c.connectMemPorts(system.membus)
-    c.mem = system.physmem
 
 root = Root(clock = '2GHz', system = system)

diff --git a/tests/configs/tsunami-simple-timing.py b/tests/configs/tsunami-simple-timing.py
index 2edf5ac3203b62c8fd11aa96c3384d638946cb98..59401c040f54c49bd21bfe933f3e87748fecf9b0 100644 (file)
--- a/tests/configs/tsunami-simple-timing.py
+++ b/tests/configs/tsunami-simple-timing.py
@@ -35,6 +35,5 @@ cpu = TimingSimpleCPU(cpu_id=0)
 system = FSConfig.makeLinuxAlphaSystem('timing')
 system.cpu = cpu
 cpu.connectMemPorts(system.membus)
-cpu.mem = system.physmem
 
 root = Root(clock = '2GHz', system = system)