0x2: decode FUNCTION_LO {
format BasicOp {
- 0x0: mfhi({{ Rd = xc->readMiscReg(Hi,0); }});
- 0x1: mthi({{ xc->setMiscReg(Hi,0,Rs); }});
- 0x2: mflo({{ Rd = xc->readMiscReg(Lo,0); }});
- 0x3: mtlo({{ xc->setMiscReg(Lo,0,Rs); }});
+ 0x0: mfhi({{ Rd = xc->readMiscReg(Hi); }});
+ 0x1: mthi({{ xc->setMiscReg(Hi,Rs); }});
+ 0x2: mflo({{ Rd = xc->readMiscReg(Lo); }});
+ 0x3: mtlo({{ xc->setMiscReg(Lo,Rs); }});
}
}
format IntOp {
0x0: mult({{
int64_t temp1 = Rs.sw * Rt.sw;
- xc->setMiscReg(Hi,0,temp1<63:32>);
- xc->setMiscReg(Lo,0,temp1<31:0>);
+ xc->setMiscReg(Hi,temp1<63:32>);
+ xc->setMiscReg(Lo,temp1<31:0>);
}});
0x1: multu({{
int64_t temp1 = Rs.uw * Rt.uw;
- xc->setMiscReg(Hi,0,temp1<63:32>);
- xc->setMiscReg(Lo,0,temp1<31:0>);
+ xc->setMiscReg(Hi,temp1<63:32>);
+ xc->setMiscReg(Lo,temp1<31:0>);
}});
0x2: div({{
- xc->setMiscReg(Hi,0,Rs.sw % Rt.sw);
- xc->setMiscReg(Lo,0,Rs.sw / Rt.sw);
+ xc->setMiscReg(Hi,Rs.sw % Rt.sw);
+ xc->setMiscReg(Lo,Rs.sw / Rt.sw);
}});
0x3: divu({{
- xc->setMiscReg(Hi,0,Rs.uw % Rt.uw);
- xc->setMiscReg(Lo,0,Rs.uw / Rt.uw);
+ xc->setMiscReg(Hi,Rs.uw % Rt.uw);
+ xc->setMiscReg(Lo,Rs.uw / Rt.uw);
}});
}
}
0x0: mfc0({{
//uint64_t reg_num = Rd.uw;
- Rt = xc->readMiscReg(RD,SEL);
+ Rt = xc->readMiscReg(RD << 5 | SEL);
}});
0x4: mtc0({{
//uint64_t reg_num = Rd.uw;
- xc->setMiscReg(RD,SEL,Rt);
+ xc->setMiscReg(RD << 5 | SEL,Rt);
}});
0x8: mftr({{
int sel;
getMiscRegIdx(MVPControl,idx,sel);
Rt.sw = xc->readMiscReg(idx,sel);
- xc->setMiscReg(idx,sel,0);
+ xc->setMiscReg(idx,sel);
}});
0x1: evpe({{
int sel;
getMiscRegIdx(VPEControl,idx,sel);
Rt.sw = xc->readMiscReg(idx,sel);
- xc->setMiscReg(idx,sel,0);
+ xc->setMiscReg(idx,sel);
}});
0x1: emt({{
int sel;
getMiscRegIdx(Status,idx,sel);
Rt.sw = xc->readMiscReg(idx,sel);
- xc->setMiscReg(idx,sel,0);
+ xc->setMiscReg(idx,sel);
}});
0x1: ei({{
0x1: decode ND {
0x0: decode TF {
format Branch {
- 0x0: bc1f({{ cond = (xc->readMiscReg(FPCR,0) == 0); }});
- 0x1: bc1t({{ cond = (xc->readMiscReg(FPCR,0) == 1); }});
+ 0x0: bc1f({{ cond = (xc->readMiscReg(FPCR) == 0); }});
+ 0x1: bc1t({{ cond = (xc->readMiscReg(FPCR) == 1); }});
}
}
0x1: decode TF {
format BranchLikely {
- 0x0: bc1fl({{ cond = (xc->readMiscReg(FPCR,0) == 0); }});
- 0x1: bc1tl({{ cond = (xc->readMiscReg(FPCR,0) == 1); }});
+ 0x0: bc1fl({{ cond = (xc->readMiscReg(FPCR) == 0); }});
+ 0x1: bc1tl({{ cond = (xc->readMiscReg(FPCR) == 1); }});
}
}
}
0x2: decode RS_LO {
0x1: decode MOVCF {
format FloatOp {
- 0x0: movfs({{if (xc->readMiscReg(FPCR,0) != CC) Fd = Fs; }});
- 0x1: movts({{if (xc->readMiscReg(FPCR,0) == CC) Fd = Fs;}});
+ 0x0: movfs({{if (xc->readMiscReg(FPCR) != CC) Fd = Fs; }});
+ 0x1: movts({{if (xc->readMiscReg(FPCR) == CC) Fd = Fs;}});
}
}
0x4: decode RS_LO {
format FloatOp {
- 0x1: cvt_d_s({{ int rnd_mode = xc->readMiscReg(FCSR,0);
+ 0x1: cvt_d_s({{ int rnd_mode = xc->readMiscReg(FCSR);
Fd = convert_and_round(Fs.sf,rnd_mode,FP_DOUBLE,FP_SINGLE);
}});
- 0x4: cvt_w_s({{ int rnd_mode = xc->readMiscReg(FCSR,0);
+ 0x4: cvt_w_s({{ int rnd_mode = xc->readMiscReg(FCSR);
Fd = convert_and_round(Fs.sf,rnd_mode,FP_WORD,FP_SINGLE);
}});
}
//only legal for 64 bit
format Float64Op {
- 0x5: cvt_l_s({{ int rnd_mode = xc->readMiscReg(FCSR,0);
+ 0x5: cvt_l_s({{ int rnd_mode = xc->readMiscReg(FCSR);
Fd = convert_and_round(Fs.sf,rnd_mode,FP_LONG,FP_SINGLE);
}});
0x2: decode RS_LO {
0x1: decode MOVCF {
format FloatOp {
- 0x0: movfd({{if (xc->readMiscReg(FPCR,0) != CC) Fd.df = Fs.df; }});
- 0x1: movtd({{if (xc->readMiscReg(FPCR,0) == CC) Fd.df = Fs.df; }});
+ 0x0: movfd({{if (xc->readMiscReg(FPCR) != CC) Fd.df = Fs.df; }});
+ 0x1: movtd({{if (xc->readMiscReg(FPCR) == CC) Fd.df = Fs.df; }});
}
}
0x4: decode RS_LO {
format FloatOp {
0x0: cvt_s_d({{
- int rnd_mode = xc->readMiscReg(FCSR,0);
+ int rnd_mode = xc->readMiscReg(FCSR);
Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_DOUBLE);
}});
0x4: cvt_w_d({{
- int rnd_mode = xc->readMiscReg(FCSR,0);
+ int rnd_mode = xc->readMiscReg(FCSR);
Fd = convert_and_round(Fs.df,rnd_mode,FP_WORD,FP_DOUBLE);
}});
}
//only legal for 64 bit
format Float64Op {
0x5: cvt_l_d({{
- int rnd_mode = xc->readMiscReg(FCSR,0);
+ int rnd_mode = xc->readMiscReg(FCSR);
Fd = convert_and_round(Fs.df,rnd_mode,FP_LONG,FP_DOUBLE);
}});
}
0x4: decode FUNCTION {
format FloatOp {
0x20: cvt_s({{
- int rnd_mode = xc->readMiscReg(FCSR,0);
+ int rnd_mode = xc->readMiscReg(FCSR);
Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_WORD);
}});
0x21: cvt_d({{
- int rnd_mode = xc->readMiscReg(FCSR,0);
+ int rnd_mode = xc->readMiscReg(FCSR);
Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_WORD);
}});
}
0x5: decode FUNCTION_HI {
format FloatOp {
0x10: cvt_s_l({{
- int rnd_mode = xc->readMiscReg(FCSR,0);
+ int rnd_mode = xc->readMiscReg(FCSR);
Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_LONG);
}});
0x11: cvt_d_l({{
- int rnd_mode = xc->readMiscReg(FCSR,0);
+ int rnd_mode = xc->readMiscReg(FCSR);
Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_LONG);
}});
}
0x2: decode RS_LO {
0x1: decode MOVCF {
format Float64Op {
- 0x0: movfps({{if (xc->readMiscReg(FPCR,0) != CC) Fd = Fs;}});
- 0x1: movtps({{if (xc->readMiscReg(FPCR,0) == CC) Fd = Fs;}});
+ 0x0: movfps({{if (xc->readMiscReg(FPCR) != CC) Fd = Fs;}});
+ 0x1: movtps({{if (xc->readMiscReg(FPCR) == CC) Fd = Fs;}});
}
}
format BasicOp {
- 0x2: movzps({{if (xc->readMiscReg(FPCR,0) != CC) Fd = Fs; }});
- 0x3: movnps({{if (xc->readMiscReg(FPCR,0) == CC) Fd = Fs; }});
+ 0x2: movzps({{if (xc->readMiscReg(FPCR) != CC) Fd = Fs; }});
+ 0x3: movnps({{if (xc->readMiscReg(FPCR) == CC) Fd = Fs; }});
}
}
0x4: decode RS_LO {
0x0: Float64Op::cvt_s_pu({{
- int rnd_mode = xc->readMiscReg(FCSR,0);
+ int rnd_mode = xc->readMiscReg(FCSR);
Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_PS_HI);
}});
}
0x5: decode RS_LO {
format Float64Op {
0x0: cvt_s_pl({{
- int rnd_mode = xc->readMiscReg(FCSR,0);
+ int rnd_mode = xc->readMiscReg(FCSR);
Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_PS_LO);
}});
0x4: pll({{ /*Fd.df = Fs<31:0> | Ft<31:0>*/}});
0x0: decode FUNCTION_LO {
format IntOp {
0x0: madd({{
- int64_t temp1 = xc->readMiscReg(Hi,0) << 32 | xc->readMiscReg(Lo,0) >> 32;
+ int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32;
temp1 = temp1 + (Rs.sw * Rt.sw);
- xc->setMiscReg(Hi,0,temp1<63:32>);
- xc->setMiscReg(Lo,0,temp1<31:0>);
+ xc->setMiscReg(Hi,temp1<63:32>);
+ xc->setMiscReg(Lo,temp1<31:0>);
}});
0x1: maddu({{
- int64_t temp1 = xc->readMiscReg(Hi,0) << 32 | xc->readMiscReg(Lo,0) >> 32;
+ int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32;
temp1 = temp1 + (Rs.uw * Rt.uw);
- xc->setMiscReg(Hi,0,temp1<63:32>);
- xc->setMiscReg(Lo,0,temp1<31:0>);
+ xc->setMiscReg(Hi,temp1<63:32>);
+ xc->setMiscReg(Lo,temp1<31:0>);
}});
0x2: mul({{ Rd.sw = Rs.sw * Rt.sw; }});
0x4: msub({{
- int64_t temp1 = xc->readMiscReg(Hi,0) << 32 | xc->readMiscReg(Lo,0) >> 32;
+ int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32;
temp1 = temp1 - (Rs.sw * Rt.sw);
- xc->setMiscReg(Hi,0,temp1<63:32>);
- xc->setMiscReg(Lo,0,temp1<31:0>);
+ xc->setMiscReg(Hi,temp1<63:32>);
+ xc->setMiscReg(Lo,temp1<31:0>);
}});
0x5: msubu({{
- int64_t temp1 = xc->readMiscReg(Hi,0) << 32 | xc->readMiscReg(Lo,0) >> 32;
+ int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32;
temp1 = temp1 - (Rs.uw * Rt.uw);
- xc->setMiscReg(Hi,0,temp1<63:32>);
- xc->setMiscReg(Lo,0,temp1<31:0>);
+ xc->setMiscReg(Hi,temp1<63:32>);
+ xc->setMiscReg(Lo,temp1<31:0>);
}});
}
}
using namespace MipsISA;
+//Function now Obsolete in current state.
+//If anyting this should return the correct miscreg index
+//but that is handled implicitly with enums anyway
void
MipsISA::getMiscRegIdx(int reg_name,int &idx, int &sel)
{
case SRSMap: idx = 12; sel = 3; break; //12-3 Shadow set IPL mapping
case Cause: idx = 13; sel = 0; break; //13-0 Cause of last general exception
case EPC: idx = 14; sel = 0; break; //14-0 Program counter at last exception
- case PRId: idx = 15; sel = 0; break; //15-0 Processor identification and revision
+ case PrId: idx = 15; sel = 0; break; //15-0 Processor identification and revision
case EBase: idx = 15; sel = 1; break; //15-1 Exception vector base register
case Config: panic("Accessing Unimplemented CP0 Register"); break;
case Config1: panic("Accessing Unimplemented CP0 Register"); break;
{
//CP0 Random Reg:
//Randomly generated index into the TLB array
- miscRegs[1][0] = 0x0000003f;
+ miscRegs[Random] = 0x0000003f;
//CP0 Wired Reg.
- miscRegs[6][0] = 0x0000000;
+ miscRegs[Wired] = 0x0000000;
//CP0 HWRENA
- miscRegs[7][0] = 0x0000000;
+ miscRegs[HWRena] = 0x0000000;
//CP0 Status Reg.
- miscRegs[12][0] = 0x0400004;
+ miscRegs[Status] = 0x0400004;
//CP0 INTCNTL
- miscRegs[12][1] = 0xfc00000;
+ miscRegs[IntCtl] = 0xfc00000;
//CP0 SRSCNTL
- miscRegs[12][2] = 0x0c00000;
+ miscRegs[SRSCtl] = 0x0c00000;
//CP0 SRSMAP
- miscRegs[12][3] = 0x0000000;
+ miscRegs[SRSMap] = 0x0000000;
//CP0 Cause
- miscRegs[13][0] = 0x0000000;
+ miscRegs[Cause] = 0x0000000;
//CP0 Processor ID
- miscRegs[15][0] = 0x0019300;
+ miscRegs[PrId] = 0x0019300;
//CP0 EBASE
- miscRegs[15][1] = 0x8000000;
+ miscRegs[EBase] = 0x8000000;
//CP0 Config Reg.
- miscRegs[16][0] = 0x80040482;
+ miscRegs[Config] = 0x80040482;
//CP0 Config 1 Reg.
- miscRegs[16][1] = 0xfee3719e;
+ miscRegs[Config1] = 0xfee3719e;
//CP0 Config 2 Reg.
- miscRegs[16][2] = 0x8000000;
+ miscRegs[Config2] = 0x8000000;
//CP0 Config 3 Reg.
- miscRegs[16][3] = 0x0000020;
+ miscRegs[Config3] = 0x0000020;
//CP0 Config 7 Reg.
- miscRegs[16][7] = 0x0000000;
+ miscRegs[Config7] = 0x0000000;
//CP0 Debug
- miscRegs[23][0] = 0x0201800;
+ miscRegs[Debug] = 0x0201800;
//CP0 PERFCNTL1
- miscRegs[25][0] = 0x0000000;
+ miscRegs[PerfCnt0] = 0x0000000;
//CP0 PERFCNTL2
- miscRegs[25][1] = 0x0000000;
+ miscRegs[PerfCnt1] = 0x0000000;
}
//Resize Coprocessor Register Banks to
// the number specified in MIPS32K VOL.III
// Chapter 8
- //
+ /*
//Cop-0 Regs. Bank 0: Index,
miscRegs[0].resize(4);
miscRegs[30].resize(1);
//Cop-0 Regs. Bank 31:
- miscRegs[31].resize(1);
+ miscRegs[31].resize(1);*/
}
// cop-0/cop-1 system control register file
typedef uint64_t MiscReg;
-//typedef MiscReg MiscRegFile[NumMiscRegs];
-
- typedef std::vector<MiscReg> MiscRegFile[NumMiscRegs];
-// typedef MiscRegBank MiscRegBanks[NumMiscRegs];
+ typedef MiscReg MiscRegFile[NumMiscRegs];
enum MiscRegTags {
//Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8
//(Register Number-Register Select) Summary of Register
//------------------------------------------------------
- Index, //0-0 Index into the TLB array
+ Index = 0, //0-0 Index into the TLB array
- MVPControl, //0-1 Per-processor register containing global
+ MVPControl = 1, //0-1 Per-processor register containing global
//MIPS® MT configuration data
- MVPConf0, //0-2 Per-processor register containing global
+ MVPConf0 = 2, //0-2 Per-processor register containing global
//MIPS® MT configuration data
- MVPConf1, //0-3 Per-processor register containing global
+ MVPConf1 = 3, //0-3 Per-processor register containing global
//MIPS® MT configuration data
- Random, //1-0 Randomly generated index into the TLB array
+ Random = 8, //1-0 Randomly generated index into the TLB array
- VPEControl, //1-1 Per-VPE register containing relatively volatile
+ VPEControl = 9, //1-1 Per-VPE register containing relatively volatile
//thread configuration data
- VPEConf0, //1-2 Per-VPE multi-thread configuration
+ VPEConf0 = 10, //1-2 Per-VPE multi-thread configuration
//information
- VPEConf1, //1-2 Per-VPE multi-thread configuration
+ VPEConf1 = 11, //1-2 Per-VPE multi-thread configuration
//information
- YQMask, //Per-VPE register defining which YIELD
+ YQMask = 12, //Per-VPE register defining which YIELD
//qualifier bits may be used without generating
//an exception
- VPESchedule,
- VPEScheFBack,
- VPEOpt,
- EntryLo0,
- TCStatus,
- TCBind,
- TCRestart,
- TCHalt,
- TCContext,
- TCSchedule,
- TCScheFBack,
- EntryLo1,
- Context,
- ContextConfig,
- //PageMask,
- PageGrain,
- Wired,
- SRSConf0,
- SRSConf1,
- SRSConf2,
- SRSConf3,
- SRSConf4,
- BadVAddr,
- Count,
- EntryHi,
- Compare,
- Status, //12-0 Processor status and control
- IntCtl, //12-1 Interrupt system status and control
- SRSCtl, //12-2 Shadow register set status and control
- SRSMap, //12-3 Shadow set IPL mapping
- Cause, //13-0 Cause of last general exception
- EPC, //14-0 Program counter at last exception
- PRId, //15-0 Processor identification and revision
- EBase, //15-1 Exception vector base register
- Config,
- Config1,
- Config2,
- Config3,
- LLAddr,
- WatchLo,
- WatchHi,
- Debug,
- TraceControl1,
- TraceControl2,
- UserTraceData,
- TraceBPC,
-
- DEPC,
-
- PerfCnt,
-
- ErrCtl,
-
- CacheErr0,
- CacheErr1,
- CacheErr2,
- CacheErr3,
-
- TagLo,
- DataLo,
- TagHi,
- DataHi,
- ErrorEPC,
- DESAVE,
+ VPESchedule = 13,
+ VPEScheFBack = 14,
+ VPEOpt = 15,
+ EntryLo0 = 16, // Bank 3: 16 - 23
+ TCStatus = 17,
+ TCBind = 18,
+ TCRestart = 19,
+ TCHalt = 20,
+ TCContext = 21,
+ TCSchedule = 22,
+ TCScheFBack = 23,
+
+ EntryLo1 = 24,// Bank 4: 24 - 31
+
+ Context = 32, // Bank 5: 32 - 39
+ ContextConfig = 33,
+
+ //PageMask = 40, //Bank 6: 40 - 47
+ PageGrain = 41,
+
+ Wired = 48, //Bank 7:48 - 55
+ SRSConf0 = 49,
+ SRSConf1 = 50,
+ SRSConf2 = 51,
+ SRSConf3 = 52,
+ SRSConf4 = 53,
+ BadVAddr = 54,
+
+ HWRena = 56,//Bank 8:56 - 63
+
+ Count = 64, //Bank 9:64 - 71
+
+ EntryHi = 72,//Bank 10:72 - 79
+
+ Compare = 80,//Bank 11:80 - 87
+
+ Status = 88,//Bank 12:88 - 96 //12-0 Processor status and control
+ IntCtl = 89, //12-1 Interrupt system status and control
+ SRSCtl = 90, //12-2 Shadow register set status and control
+ SRSMap = 91, //12-3 Shadow set IPL mapping
+
+ Cause = 97,//97-104 //13-0 Cause of last general exception
+
+ EPC = 105,//105-112 //14-0 Program counter at last exception
+
+ PrId = 113//113-120, //15-0 Processor identification and revision
+ EBase = 114, //15-1 Exception vector base register
+
+ Config = 121,//121-128
+ Config1 = 122,
+ Config2 = 123,
+ Config3 = 124,
+ Config6 = 127,
+ Config7 = 128,
+
+
+ LLAddr = 129,//129-136
+
+ WatchLo0 = 137,//137-144
+ WatchLo1 = 138,
+ WatchLo2 = 139,
+ WatchLo3 = 140,
+ WatchLo4 = 141,
+ WatchLo5 = 142,
+ WatchLo6 = 143,
+ WatchLo7 = 144,
+
+ WatchHi0 = 145,//145-152
+ WatchHi1 = 146,
+ WatchHi2 = 147,
+ WatchHi3 = 148,
+ WatchHi4 = 149,
+ WatchHi5 = 150,
+ WatchHi6 = 151,
+ WatchHi7 = 152,
+
+ XCContext64 = 153,//153-160
+
+ //161-168
+
+ //169-176
+
+ Debug = 177, //177-184
+ TraceControl1 = 178,
+ TraceControl2 = 179,
+ UserTraceData = 180,
+ TraceBPC = 181,
+
+ DEPC = 185,//185-192
+
+ PerfCnt0 = 193,//193 - 200
+ PerfCnt1 = 194,
+ PerfCnt2 = 195,
+ PerfCnt3 = 196,
+ PerfCnt4 = 197,
+ PerfCnt5 = 198,
+ PerfCnt6 = 199,
+ PerfCnt7 = 200,
+
+ ErrCtl = 201, //201 - 208
+
+ CacheErr0 = 209, //209 - 216
+ CacheErr1 = 210,
+ CacheErr2 = 211,
+ CacheErr3 = 212,
+
+ TagLo0 = 217,//217 - 224
+ TagLo2 = 219,
+ TagLo4 = 221,
+ TagLo6 = 223,
+
+ DataLo1 = 226,//225 - 232
+ DataLo3 = 228,
+ DataLo5 = 220,
+ DataLo7 = 232,
+
+ TagHi0 = 233,//233 - 240
+ TagHi2 = 235,
+ TagHi4 = 237,
+ TagHi6 = 239,
+
+ DataHi0 = 241,//241 - 248
+ DataHi2 = 243,
+ DataHi4 = 245,
+ DataHi6 = 247,
+
+ ErrorEPC = 249,//249 - 256
+
+ DESAVE = 257,
//More Misc. Regs
Hi,
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