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diff --git a/openpower/isa/svfixedarith.mdwn b/openpower/isa/svfixedarith.mdwn
index 1a1e5fe6851b1c029ecf3361fa21b2ecb507413b..5ed1d283f163f3bbd9a97ba97cfc6d817e1cd996 100644 (file)
--- a/openpower/isa/svfixedarith.mdwn
+++ b/openpower/isa/svfixedarith.mdwn
@@ -1,38 +1,6 @@
-# Multiply Twin Doubleword
+# Twin Multiply and Add Doubleword
 
-XO-Form
-
-* mulxd RT,RA,RB
-
-Pseudo-code:
-
-    prod[0:(XLEN*2)-1] <- MULS((RA), (RB))
-    RT <- prod[XLEN:(XLEN*2)-1]
-    RS <- prod[0:XLEN-1]
-
-Special Registers Altered:
-
-    None
-
-# Multiply Twin Doubleword Unsigned
-
-XO-Form
-
-* mulxdu RT,RA,RB
-
-Pseudo-code:
-
-    prod[0:(XLEN*2)-1] <- (RA) * (RB)
-    RT <- prod[XLEN:(XLEN*2)-1]
-    RS <- prod[0:XLEN-1]
-
-Special Registers Altered:
-
-    None
-
-# Twin Multiply and Add  Doubleword
-
-* maddx RT,RA,RB,RC
+* madded RT,RA,RB,RC
 
 Pseudo-code:
 
@@ -50,35 +18,18 @@ Special Registers Altered:
 
 # Twin Multiply and Subtract Doubleword
 
-* msubx RT,RA,RB,RC
+* msubed RT,RA,RB,RC
 
 Pseudocode:
 
-    <!-- (RS=RT+VL for SVP64, RS=RT+1 for scalar) />
-    prod[0:127] = (RA) * (RB)
-    sub[0:127] = EXTZ(RC) - prod
+    <!-- SVP64: RA,RB,RC,RT have EXTRA2, RS as below   -->
+    <!-- bit 8 of EXTRA is clear: RS.[s|v]=RT.[s|v]+VL -->
+    <!-- bit 8 of EXTRA is set  : RS.[s|v]=RC.[s|v]    -->
+    prod[0:127] <- (RA) * (RB)
+    sub[0:127] <- EXTZ(RC) - prod
     RT <- sub[64:127]
     RS <- sub[0:63]
 
 Special Registers Altered:
 
     None
-
-# Twin Add Carry Subtract Doubleword
-
-* weirdaddx RT,RA,RB
-
-Pseudocode:
-
-    <!-- (RS=RB+VL for SVP64, RS=RB+1 for scalar) />
-    <!-- RA both an input and output -->
-    cat[0:127] = (RS) || (RB)
-    sum[0:127] = cat + EXTZ(RA) - 1
-    rhi[0:63] = sum[0:63]
-    if (RA)[0:62] = [0]*63 then rhi = rhi + 1
-    RA = rhi
-    RT = sum[64:127]
-
-Special Registers Altered:
-
-    None