platforms/versa_ecp5: add spiflash pads

diff --git a/litex/boards/platforms/versa_ecp5.py b/litex/boards/platforms/versa_ecp5.py
index b91110b53f9ff9870b6ef3d656cd516fd698cd1b..0b27a657a25790f77b8c9fc52a72b017e45b032e 100644 (file)
--- a/litex/boards/platforms/versa_ecp5.py
+++ b/litex/boards/platforms/versa_ecp5.py
@@ -35,6 +35,21 @@ _io = [
         Subsignal("tx", Pins("A11"), IOStandard("LVCMOS33")),
     ),
 
+    ("spiflash", 0, # clock needs to be accessed through USRMCLK
+        Subsignal("cs_n", Pins("R2")),
+        Subsignal("mosi", Pins("W2")),
+        Subsignal("miso", Pins("V2")),
+        Subsignal("wp", Pins("Y2")),
+        Subsignal("hold", Pins("W1")),
+        IOStandard("LVCMOS33"),
+    ),
+
+    ("spiflash4x", 0, # clock needs to be accessed through USRMCLK
+        Subsignal("cs_n", Pins("R2")),
+        Subsignal("dq", Pins("W2 V2 Y2 W1")),
+        IOStandard("LVCMOS33")
+    ),
+
     ("ddram", 0,
         Subsignal("a", Pins(
             "P2 C4 E5 F5 B3 F4 B5 E4",