r600g,radeonsi: consolidate r600_texture structures
authorMarek Olšák <marek.olsak@amd.com>
Sat, 21 Sep 2013 18:14:52 +0000 (20:14 +0200)
committerMarek Olšák <marek.olsak@amd.com>
Sun, 29 Sep 2013 13:18:08 +0000 (15:18 +0200)
src/gallium/drivers/r600/r600_resource.h
src/gallium/drivers/radeon/r600_pipe_common.h
src/gallium/drivers/radeonsi/r600_resource.h

index 0c569b3a74e510036193c0845c4dad34eeaa7968..a3ccdb0c638319ca0f0f4ede94561810cb833139 100644 (file)
@@ -34,30 +34,6 @@ struct r600_resource_global {
        struct compute_memory_item *chunk;
 };
 
-struct r600_texture {
-       struct r600_resource            resource;
-
-       unsigned                        pitch_override;
-       unsigned                        size;
-       bool                            non_disp_tiling;
-       bool                            is_depth;
-       unsigned                        dirty_level_mask; /* each bit says if that mipmap is compressed */
-       struct r600_texture             *flushed_depth_texture;
-       boolean                         is_flushing_texture;
-       struct radeon_surface           surface;
-
-       /* Colorbuffer compression and fast clear. */
-       struct r600_fmask_info          fmask;
-       struct r600_cmask_info          cmask;
-
-       struct r600_resource            *htile;
-       /* use htile only for first level */
-       float                           depth_clear;
-
-       struct r600_resource            *cmask_buffer;
-       unsigned                        color_clear_value[2];
-};
-
 struct r600_surface {
        struct pipe_surface             base;
 
index 0bd696a8818c8ed54f71466c096a6fe39f5dbcae..63439655fd2fac86fb0ff5113b56dca32b8a3d55 100644 (file)
@@ -105,6 +105,31 @@ struct r600_cmask_info {
        unsigned slice_tile_max;
 };
 
+struct r600_texture {
+       struct r600_resource            resource;
+
+       unsigned                        size;
+       unsigned                        pitch_override;
+       bool                            is_depth;
+       unsigned                        dirty_level_mask; /* each bit says if that mipmap is compressed */
+       struct r600_texture             *flushed_depth_texture;
+       boolean                         is_flushing_texture;
+       struct radeon_surface           surface;
+
+       /* Colorbuffer compression and fast clear. */
+       struct r600_fmask_info          fmask;
+       struct r600_cmask_info          cmask;
+
+       struct r600_resource            *htile;
+       float                           depth_clear; /* use htile only for first level */
+
+       struct r600_resource            *cmask_buffer;
+       unsigned                        color_clear_value[2];
+
+       bool                            non_disp_tiling; /* R600-Cayman only */
+       unsigned                        mipmap_shift;
+};
+
 struct r600_common_screen {
        struct pipe_screen              b;
        struct radeon_winsys            *ws;
index ab9ddbe010a496e1609247a54258730a9d3f3ca4..116287ccc3353530d4827434198444e77ce403ce 100644 (file)
 #ifndef R600_RESOURCE_H
 #define R600_RESOURCE_H
 
-#include "util/u_transfer.h"
-
-struct r600_texture {
-       struct r600_resource            resource;
-
-       unsigned                        size;
-       unsigned                        pitch_override;
-       unsigned                        is_depth;
-       unsigned                        dirty_level_mask; /* each bit says if that miplevel is dirty */
-       struct r600_texture             *flushed_depth_texture;
-       boolean                         is_flushing_texture;
-       struct radeon_surface           surface;
-       unsigned mipmap_shift;
-
-       /* Colorbuffer compression and fast clear. */
-       struct r600_fmask_info          fmask;
-       struct r600_cmask_info          cmask;
-};
+#include "../radeon/r600_pipe_common.h"
 
 struct r600_surface {
        struct pipe_surface             base;