clean up (thanks to Sebastien)

diff --git a/lib/sata/k7sataphy/clocking.py b/lib/sata/k7sataphy/clocking.py
index d5a93d97e32ca637db45b8796b319e049363e89f..d257c7dc04061b660393553161e505a32bf57277 100644 (file)
--- a/lib/sata/k7sataphy/clocking.py
+++ b/lib/sata/k7sataphy/clocking.py
@@ -17,9 +17,9 @@ class K7SATAPHYReconfig(Module):
                drp = DRPBus()
                self.comb += \
                        If(drp_sel,
-                               Record.connect(drp, mmcm_drp),
+                               drp.connect(mmcm_drp)
                        ).Else(
-                               Record.connect(drp, channel_drp)
+                               drp.connect(channel_drp)
                        )
 
 class K7SATAPHYClocking(Module):

diff --git a/lib/sata/k7sataphy/ctrl.py b/lib/sata/k7sataphy/ctrl.py
index 873defbe9f2a5cb0c9b3d630e66c5b17c87b28c0..7f63b0f3344b1c089d2a69d02b108d7071bc3184 100644 (file)
--- a/lib/sata/k7sataphy/ctrl.py
+++ b/lib/sata/k7sataphy/ctrl.py
@@ -9,15 +9,13 @@ from lib.sata.k7sataphy.std import *
 # Todo:
 # rx does not use the same clock, need to resynchronize signals.
 
-def us(t, speed="SATA3", margin=True):
+def us(t, speed="SATA3"):
        clk_freq = {
                "SATA3" :       300*1000000,
                "SATA2" :       150*1000000,
                "SATA1" :        75*1000000
        }
        clk_period_us = 1000000/clk_freq[speed]
-       if margin:
-               t += clk_period_us/2
        return ceil(t/clk_period_us)
 
 class K7SATAPHYHostCtrl(Module):