power_insn: fix verbose assembly extra info

diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py
index 0a2a13c149ff4c88485123886b290525b91e292d..7d779ca8d00616e9c6188b0876752b035e429200 100644 (file)
--- a/src/openpower/decoder/power_insn.py
+++ b/src/openpower/decoder/power_insn.py
@@ -1295,12 +1295,12 @@ class ExtendableOperand(DynamicOperand):
             yield f"{indent}{indent}{int(value):0{value.bits}b}"
             yield f"{indent}{indent}{', '.join(span)}"
             if isinstance(insn, SVP64Instruction):
-                extra_idx = self.extra_idx
-                if self.record.etype is _SVEType.NONE:
-                    yield f"{indent}{indent}extra[none]"
-                else:
-                    etype = repr(self.record.etype).lower()
-                    yield f"{indent}{indent}{etype}{extra_idx!r}"
+                for extra_idx in frozenset(self.extra_idx):
+                    if self.record.etype is _SVEType.NONE:
+                        yield f"{indent}{indent}extra[none]"
+                    else:
+                        etype = repr(self.record.etype).lower()
+                        yield f"{indent}{indent}{etype}{extra_idx!r}"
         else:
             vector = "*" if vector else ""
             yield f"{vector}{prefix}{int(value)}"