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Merge pull request #453 from dh73/master
authorClifford Wolf <clifford@clifford.at>
Sat, 18 Nov 2017 08:56:36 +0000 (09:56 +0100)
committerGitHub <noreply@github.com>
Sat, 18 Nov 2017 08:56:36 +0000 (09:56 +0100)
Updating Intel FPGA subsystem with Cyclone 10, minor changes in examples/intel directory and Speedster cells


Trivial merge