[Patch AArch64] Improve SIMD concatenation with zeroes

gcc/

	* config/aarch64/aarch64-simd.md (*aarch64_combinez<mode>): Add
	alternatives for reads from memory and moves from general-purpose
	registers.
	(*aarch64_combinez_be<mode>): Likewise.

gcc/testsuite/

	* gcc.target/aarch64/vect_combine_zeroes_1.c: New.

From-SVN: r228374

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index b9d21ec119291464cc6a21b158587833aaebbe32..6eeb740e59012445f5112512e4405b5b811615a5 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2015-10-02  James Greenhalgh  <james.greenhalgh@arm.com>
+
+       * config/aarch64/aarch64-simd.md (*aarch64_combinez<mode>): Add
+       alternatives for reads from memory and moves from general-purpose
+       registers.
+       (*aarch64_combinez_be<mode>): Likewise.
+
 2015-10-02  Kai Tietz  <ktietz70@googlemail.com>
 
        PR target/51726

diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 541faf982effc7195a5f8d0d82738f76a7e04b4b..6a2ab619d76c28533ba9c668fb807ae07ed9719d 100644 (file)
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -2530,23 +2530,33 @@
 ;; dest vector.
 
 (define_insn "*aarch64_combinez<mode>"
-  [(set (match_operand:<VDBL> 0 "register_operand" "=&w")
+  [(set (match_operand:<VDBL> 0 "register_operand" "=w,w,w")
         (vec_concat:<VDBL>
-          (match_operand:VD_BHSI 1 "register_operand" "w")
-          (match_operand:VD_BHSI 2 "aarch64_simd_imm_zero" "Dz")))]
+          (match_operand:VD_BHSI 1 "general_operand" "w,r,m")
+          (match_operand:VD_BHSI 2 "aarch64_simd_imm_zero" "Dz,Dz,Dz")))]
   "TARGET_SIMD && !BYTES_BIG_ENDIAN"
-  "mov\\t%0.8b, %1.8b"
-  [(set_attr "type" "neon_move<q>")]
+  "@
+   mov\\t%0.8b, %1.8b
+   fmov\t%d0, %1
+   ldr\\t%d0, %1"
+  [(set_attr "type" "neon_move<q>, neon_from_gp, neon_load1_1reg")
+   (set_attr "simd" "yes,*,yes")
+   (set_attr "fp" "*,yes,*")]
 )
 
 (define_insn "*aarch64_combinez_be<mode>"
-  [(set (match_operand:<VDBL> 0 "register_operand" "=&w")
+  [(set (match_operand:<VDBL> 0 "register_operand" "=w,w,w")
         (vec_concat:<VDBL>
-          (match_operand:VD_BHSI 2 "aarch64_simd_imm_zero" "Dz")
-          (match_operand:VD_BHSI 1 "register_operand" "w")))]
+          (match_operand:VD_BHSI 2 "aarch64_simd_imm_zero" "Dz,Dz,Dz")
+          (match_operand:VD_BHSI 1 "general_operand" "w,r,m")))]
   "TARGET_SIMD && BYTES_BIG_ENDIAN"
-  "mov\\t%0.8b, %1.8b"
-  [(set_attr "type" "neon_move<q>")]
+  "@
+   mov\\t%0.8b, %1.8b
+   fmov\t%d0, %1
+   ldr\\t%d0, %1"
+  [(set_attr "type" "neon_move<q>, neon_from_gp, neon_load1_1reg")
+   (set_attr "simd" "yes,*,yes")
+   (set_attr "fp" "*,yes,*")]
 )
 
 (define_expand "aarch64_combine<mode>"

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 503e5151d2a8215776932092a9f09aca5150ace2..1028cf765ee386fc59519421f410eb6690a3ba78 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2015-10-02  James Greenhalgh  <james.greenhalgh@arm.com>
+
+       * gcc.target/aarch64/vect_combine_zeroes_1.c: New.
+
 2015-10-02  Kai Tietz  <ktietz70@googlemail.com>
 
        PR target/51726

diff --git a/gcc/testsuite/gcc.target/aarch64/vect_combine_zeroes_1.c b/gcc/testsuite/gcc.target/aarch64/vect_combine_zeroes_1.c
new file mode 100644 (file)
index 0000000..6257fa9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/vect_combine_zeroes_1.c
@@ -0,0 +1,24 @@
+/* { dg-options "-O2 --save-temps" } */
+
+#include "arm_neon.h"
+
+int32x4_t
+foo (int32x2_t *x)
+{
+  int32x2_t i = *x;
+  int32x2_t zeroes = vcreate_s32 (0l);
+  int32x4_t ret = vcombine_s32 (i, zeroes);
+  return ret;
+}
+
+int32x4_t
+bar (int64_t x)
+{
+  int32x2_t i = vcreate_s32 (x);
+  int32x2_t zeroes = vcreate_s32 (0l);
+  int32x4_t ret = vcombine_s32 (i, zeroes);
+  return ret;
+}
+
+/* { dg-final { scan-assembler-not "mov\tv\[0-9\]+.8b, v\[0-9\]+.8b" } } */
+