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diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
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--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
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 # Condition Register SVP64 Operations
 
 Condition Register Fields are only 4 bits wide: this presents some
-interesting conceptual challenges for SVP64, oarticularly with respect to element
+interesting conceptual challenges for SVP64, particularly with respect to element
 width (which is clearly meaningless). Likewise, arithmetic saturation
+(an important part of Arithmetic SVP64)
 has no meaning. Consequently an alternative Mode Format is required.
 
 This alternative mapping **only** applies to instructions that **only**