add shaddw

diff --git a/openpower/isa/bitmanip.mdwn b/openpower/isa/bitmanip.mdwn
index 79aeaa18dc6f974f777354068c9bcb2cae8d3860..6942ff5f26895418d13aeaf3c90767a377a786c9 100644 (file)
--- a/openpower/isa/bitmanip.mdwn
+++ b/openpower/isa/bitmanip.mdwn
@@ -118,6 +118,25 @@ Special Registers Altered:
 
     CR0                    (if Rc=1)
 
+# Add With Shift By Immediate Word
+
+Z23-Form
+
+* shaddw RT,RA,RB,sm (Rc=0)
+* shaddw. RT,RA,RB,sm (Rc=1)
+
+Pseudo-code:
+
+    n <- ([0]*(XLEN/2)) || (RB)[XLEN/2:XLEN-1]
+    if (RB)[XLEN/2] = 1 then
+        n[0:XLEN/2-1] <- [1]*(XLEN/2)
+    m <- ((0b0 || sm) + 1)
+    RT <- (n[m:XLEN-1] || [0]*m) + (RA)
+
+Special Registers Altered:
+
+    CR0                    (if Rc=1)
+
 # Add With Shift By Immediate Unsigned Word
 
 Z23-Form

diff --git a/openpower/isatables/RM-1P-2S1D.csv b/openpower/isatables/RM-1P-2S1D.csv
index d4fd58ff65dc76347a78d4fc456a947f3fa2a03d..ee27bbab8894355a9c830be821052157302633f7 100644 (file)
--- a/openpower/isatables/RM-1P-2S1D.csv
+++ b/openpower/isatables/RM-1P-2S1D.csv
@@ -26,6 +26,7 @@ modsw,NORMAL,,1P,EXTRA3,NO,d:RT,s:RA,s:RB,0,RA,RB,0,RT,0,0,0
 30/6=fmrgew,NORMAL,,1P,EXTRA3,NO,d:FRT,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,0,0
 rlwnm,NORMAL,,1P,EXTRA3,NO,d:RA;d:CR0,s:RB,s:RS,0,0,RB,RS,RA,0,CR0,0
 shadd,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
+shaddw,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
 shadduw,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
 minu,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
 maxu,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0

diff --git a/openpower/isatables/minor_22.csv b/openpower/isatables/minor_22.csv
index e696ad4a33818db90c2a49a008c004b4fc76bfb6..38ddefe1d943361cc8358dec06d5469a6162401f 100644 (file)
--- a/openpower/isatables/minor_22.csv
+++ b/openpower/isatables/minor_22.csv
@@ -32,6 +32,7 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou
 0001001110-,ALU,OP_MINMAX,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,minu,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
 1101001110-,ALU,OP_AVGADD,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,avgadd,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
 --01101110-,ALU,OP_SHADD,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,shadd,Z23,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+--10101110-,ALU,OP_SHADD,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,shaddw,Z23,,1,unofficial until submitted and approved/renumbered by the opf isa wg
 --11101110-,ALU,OP_SHADD,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,shadduw,Z23,,1,unofficial until submitted and approved/renumbered by the opf isa wg
 1011110110-,ALU,OP_ABSDIFF,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,absdu,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
 1001110110-,ALU,OP_ABSDIFF,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,absds,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 7e656d83527453dea99594e432a64c63a364f2c8..9917e3a04fd31709917bdc636827eb0756d14ded 100644 (file)
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -1895,7 +1895,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop):
                        'absdu', 'absds', 'absdacs', 'absdacu', 'avgadd',
                        'fmvis', 'fishmv', 'pcdec', "maddedu", "divmod2du",
                        "dsld", "dsrd", "maddedus",
-                       "shadd", "shadduw",
+                       "shadd", "shaddw", "shadduw",
                        ]:
             illegal = False
             ins_name = dotstrp

diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py
index 90a91e1dba50b4af8da59b9628d5d4c4ca634bdd..06817dabca4c14cdcabadb28c3e81cec4b9e4e92 100644 (file)
--- a/src/openpower/decoder/power_enums.py
+++ b/src/openpower/decoder/power_enums.py
@@ -769,7 +769,7 @@ _insns = [
     "svshape2",  # https://libre-soc.org/openpower/sv/remap/discussion TODO
     "svstep",  # https://libre-soc.org/openpower/sv/setvl
     "sim_cfg",
-    "shadd", "shadduw",
+    "shadd", "shaddw", "shadduw",
     "slbia", "sld", "slw", "srad", "sradi",
     "sraw", "srawi", "srd", "srw",
     "stb", "stbcix", "stbcx", "stbu", "stbux", "stbx",

diff --git a/src/openpower/sv/trans/test_pysvp64dis.py b/src/openpower/sv/trans/test_pysvp64dis.py
index ed1743242523856b5d459aefaaa3a1499e97772f..106498ffdcaea26893e9e17bddd2fdc3f2a44ba5 100644 (file)
--- a/src/openpower/sv/trans/test_pysvp64dis.py
+++ b/src/openpower/sv/trans/test_pysvp64dis.py
@@ -424,7 +424,7 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def test_31_shadd_shadduw(self):
+    def test_31_shadd_shaddw_shadduw(self):
         expected = [
                     "shadd 31,0,0,0",
                     "shadd 0,31,0,0",
@@ -434,6 +434,14 @@ class SVSTATETestCase(unittest.TestCase):
                     "shadd. 0,31,0,0",
                     "shadd. 0,0,31,0",
                     "shadd. 0,0,0,3",
+                    "shaddw 31,0,0,0",
+                    "shaddw 0,31,0,0",
+                    "shaddw 0,0,31,0",
+                    "shaddw 0,0,0,3",
+                    "shaddw. 31,0,0,0",
+                    "shaddw. 0,31,0,0",
+                    "shaddw. 0,0,31,0",
+                    "shaddw. 0,0,0,3",
                     "shadduw 31,0,0,0",
                     "shadduw 0,31,0,0",
                     "shadduw 0,0,31,0",

diff --git a/src/openpower/test/bigint/bigint_cases.py b/src/openpower/test/bigint/bigint_cases.py
index 3c83fd5760cbdf4b97bc2321545f7e0373871ff1..260d8b7cdfc366d0cf846dbb2f93ed7729aa2090 100644 (file)
--- a/src/openpower/test/bigint/bigint_cases.py
+++ b/src/openpower/test/bigint/bigint_cases.py
@@ -137,6 +137,23 @@ class BigIntCases(TestAccumulatorBase):
                 e.intregs[3] = RT
                 self.add_case(prog, gprs, expected=e)
 
+    def case_shaddw(self):
+        for sm in range(4):
+            with self.subTest(sm=sm):
+                insn = ("shaddw 3,4,5,%d" % sm)
+                prog = Program(list(SVP64Asm([insn])), False)
+                gprs = [0] * 32
+                gprs[3] = 0x01234567890abcde
+                RA = gprs[4] = 0xf00dcafedeadbeef
+                RB = gprs[5] = 0xabadbabedefec8ed
+                RB_i32 = RB & _MASK32
+                if RB_i32 >> 31:
+                    RB_i32 -= 1 << 32
+                RT = ((((RB_i32 << (sm+1)) & _MASK64) + RA) & _MASK64)
+                e = ExpectedState(pc=4, int_regs=gprs)
+                e.intregs[3] = RT
+                self.add_case(prog, gprs, expected=e)
+
     def case_shadduw(self):
         for sm in range(4):
             with self.subTest(sm=sm):