platforms/versa_ecp5: add ddram pins

diff --git a/litex/boards/platforms/versa_ecp5.py b/litex/boards/platforms/versa_ecp5.py
index 18aadfdef4adea9b4c18cf9f7c630a7a0f8d3386..dbfc26cf587cf5e4d94983b3c51552a7e024a296 100644 (file)
--- a/litex/boards/platforms/versa_ecp5.py
+++ b/litex/boards/platforms/versa_ecp5.py
@@ -33,6 +33,32 @@ _io = [
         Subsignal("tx", Pins("A11"), IOStandard("LVCMOS33")),
     ),
 
+    ("ddram", 0,
+        Subsignal("a", Pins(
+            "P2 C4 E5 F5 B3 F4 B5 E4",
+            "C5 E3 D5 B4 C3"),
+            IOStandard("SSTL135_I")),
+        Subsignal("ba", Pins("P5 N3 M3"), IOStandard("SSTL135_I")),
+        Subsignal("ras_n", Pins("P1"), IOStandard("SSTL135_I")),
+        Subsignal("cas_n", Pins("L1"), IOStandard("SSTL135_I")),
+        Subsignal("we_n", Pins("M1"), IOStandard("SSTL135_I")),
+        Subsignal("cs_n", Pins("K1"), IOStandard("SSTL135_I")),
+        Subsignal("dm", Pins("J4 H5"), IOStandard("SSTL135_I")),
+        Subsignal("dq", Pins(
+            "L5 F1 K4 G1 L4 H1 G2 J3",
+            "D1 C1 E2 C2 F3 A2 E1 B1"),
+            IOStandard("SSTL135_I"),
+            Misc("TERMINATION=75")),
+        Subsignal("dqs_p", Pins("K2 H4"), IOStandard("SSTL135D_I"), Misc("TERMINATION=OFF"), Misc("DIFFRESISTOR=100")),
+        Subsignal("dqs_n", Pins("J1 G5"), IOStandard("SSTL135D_I")),
+        Subsignal("clk_p", Pins("M4"), IOStandard("SSTL135D_I")),
+        Subsignal("clk_n", Pins("N5"), IOStandard("SSTL135D_I")),
+        Subsignal("cke", Pins("N2"), IOStandard("SSTL135_I")),
+        Subsignal("odt", Pins("L2"), IOStandard("SSTL135_I")),
+        Subsignal("reset_n", Pins("N4"), IOStandard("SSTL135_I")),
+        Misc("SLEWRATE=FAST"),
+    ),
+
     ("eth_clocks", 0,
         Subsignal("tx", Pins("P19")),
         Subsignal("rx", Pins("L20")),