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Update CHANGELOG
authorEddie Hung <eddie@fpgeh.com>
Wed, 12 Jun 2019 23:54:12 +0000 (16:54 -0700)
committerEddie Hung <eddie@fpgeh.com>
Wed, 12 Jun 2019 23:54:12 +0000 (16:54 -0700)
CHANGELOG patch | blob | history

diff --git a/CHANGELOG b/CHANGELOG
index 839fefcf1d0b57888408eb5dc20bc8dae561733f..6e3faa9ff98a66bf1228926ead26ea67bd2787dc 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -17,6 +17,7 @@ Yosys 0.8 .. Yosys 0.8-dev
     - Added "rename -src"
     - Added "equiv_opt" pass
     - Added "read_aiger" frontend
+    - Added "abc9" pass (experimental, accessible using synth_xilinx -abc9 and synth_ice40 -abc9)
     - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"