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stats: Add a boat load of stats to the SPARC solaris boot regression.
authorGabe Black <gabeblack@google.com>
Tue, 4 Apr 2017 07:56:29 +0000 (00:56 -0700)
committerGabe Black <gabeblack@google.com>
Wed, 5 Apr 2017 18:33:35 +0000 (18:33 +0000)
A large number of stats were added by the following change:

    commit 5350879f499470a2683dfec6cff021dd7ac20fa6
    Author: David Guillen Fandos <david.guillen@arm.com>
    Date:   Mon Jun 6 17:16:43 2016 +0100

        pwr: Add power states to ClockedObject

Change-Id: Iec32bb7f701db0a09be26fe5ffb2812385f972c2
Reviewed-on: https://gem5-review.googlesource.com/2642
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini patch | blob | history
tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.json patch | blob | history
tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout patch | blob | history
tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt patch | blob | history

diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
index 76f5cbc6728067aea1f29aa3dd58dd5afa75a177..8fe2ef1b73e009e9c7d815076b107856c1dae2d4 100644 (file)
--- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
+++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
@@ -14,13 +14,14 @@ children=bridge clk_domain cpu cpu_clk_domain disk0 dvfs_handler hypervisor_desc
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 exit_on_work_items=false
 hypervisor_addr=1099243257856
-hypervisor_bin=/dist/m5/system/binaries/q_new.bin
+hypervisor_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/q_new.bin
 hypervisor_desc=system.hypervisor_desc
 hypervisor_desc_addr=133446500352
-hypervisor_desc_bin=/dist/m5/system/binaries/1up-hv.bin
+hypervisor_desc_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/1up-hv.bin
 init_param=0
 kernel=
 kernel_addr_check=true
@@ -34,17 +35,22 @@ multi_thread=false
 num_work_ids=16
 nvram=system.nvram
 nvram_addr=133429198848
-nvram_bin=/dist/m5/system/binaries/nvram1
+nvram_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/nvram1
 openboot_addr=1099243716608
-openboot_bin=/dist/m5/system/binaries/openboot_new.bin
+openboot_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/openboot_new.bin
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=2000000000
+p_state_clk_gate_min=2
 partition_desc=system.partition_desc
 partition_desc_addr=133445976064
-partition_desc_bin=/dist/m5/system/binaries/1up-md.bin
-readfile=/z/stever/hg/gem5/tests/halt.sh
+partition_desc_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/1up-md.bin
+readfile=/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh
 reset_addr=1099243192320
-reset_bin=/dist/m5/system/binaries/reset_new.bin
+reset_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/reset_new.bin
 rom=system.rom
 symbolfile=
+thermal_components=
+thermal_model=Null
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -57,8 +63,12 @@ system_port=system.membus.slave[0]
 [system.bridge]
 type=Bridge
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 delay=100
 eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=2000000000
+p_state_clk_gate_min=2
 ranges=133412421632:133412421639 134217728000:554050781183 644245094400:652835028991 725849473024:1095485095935 1099255955456:1099255955463
 req_size=16
 resp_size=16
@@ -80,6 +90,7 @@ branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=0
+default_p_state=UNDEFINED
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -96,6 +107,9 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=2000000000
+p_state_clk_gate_min=2
 profile=0
 progress_interval=0
 simpoint_start_insts=
@@ -144,8 +158,12 @@ voltage_domain=system.voltage_domain
 type=MmDisk
 children=image
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 image=system.disk0.image
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=2000000000
+p_state_clk_gate_min=2
 pio_addr=134217728000
 pio_latency=200
 system=system
@@ -163,7 +181,7 @@ table_size=65536
 [system.disk0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/dist/m5/system/disks/disk.s10hw2
+image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/disk.s10hw2
 read_only=true
 
 [system.dvfs_handler]
@@ -179,11 +197,15 @@ type=SimpleMemory
 bandwidth=0.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
 latency=60
 latency_var=0
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=2000000000
+p_state_clk_gate_min=2
 range=133446500352:133446508543
 port=system.membus.master[5]
 
@@ -195,9 +217,13 @@ sys=system
 [system.iobus]
 type=NoncoherentXBar
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=1
 frontend_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=2000000000
+p_state_clk_gate_min=2
 response_latency=2
 use_default_range=false
 width=16
@@ -208,9 +234,14 @@ slave=system.bridge.master
 type=CoherentXBar
 children=badaddr_responder
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=2000000000
+p_state_clk_gate_min=2
+point_of_coherency=true
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4
@@ -224,8 +255,12 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
 [system.membus.badaddr_responder]
 type=IsaFake
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 fake_mem=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=2000000000
+p_state_clk_gate_min=2
 pio_addr=0
 pio_latency=200
 pio_size=8
@@ -244,11 +279,15 @@ type=SimpleMemory
 bandwidth=0.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
 latency=60
 latency_var=0
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=2000000000
+p_state_clk_gate_min=2
 range=133429198848:133429207039
 port=system.membus.master[4]
 
@@ -257,11 +296,15 @@ type=SimpleMemory
 bandwidth=0.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
 latency=60
 latency_var=0
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=2000000000
+p_state_clk_gate_min=2
 range=133445976064:133445984255
 port=system.membus.master[6]
 
@@ -270,11 +313,15 @@ type=SimpleMemory
 bandwidth=0.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
 latency=60
 latency_var=0
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=2000000000
+p_state_clk_gate_min=2
 range=1048576:68157439
 port=system.membus.master[7]
 
@@ -283,11 +330,15 @@ type=SimpleMemory
 bandwidth=0.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
 latency=60
 latency_var=0
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=2000000000
+p_state_clk_gate_min=2
 range=2147483648:2415919103
 port=system.membus.master[8]
 
@@ -296,11 +347,15 @@ type=SimpleMemory
 bandwidth=0.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
 latency=60
 latency_var=0
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=2000000000
+p_state_clk_gate_min=2
 range=1099243192320:1099251580927
 port=system.membus.master[3]
 
@@ -314,8 +369,12 @@ system=system
 [system.t1000.fake_clk]
 type=IsaFake
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 fake_mem=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=2000000000
+p_state_clk_gate_min=2
 pio_addr=644245094400
 pio_latency=200
 pio_size=4294967296
@@ -332,8 +391,12 @@ pio=system.iobus.master[0]
 [system.t1000.fake_jbi]
 type=IsaFake
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 fake_mem=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=2000000000
+p_state_clk_gate_min=2
 pio_addr=549755813888
 pio_latency=200
 pio_size=4294967296
@@ -350,8 +413,12 @@ pio=system.iobus.master[11]
 [system.t1000.fake_l2_1]
 type=IsaFake
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 fake_mem=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=2000000000
+p_state_clk_gate_min=2
 pio_addr=725849473024
 pio_latency=200
 pio_size=8
@@ -368,8 +435,12 @@ pio=system.iobus.master[2]
 [system.t1000.fake_l2_2]
 type=IsaFake
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 fake_mem=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=2000000000
+p_state_clk_gate_min=2
 pio_addr=725849473088
 pio_latency=200
 pio_size=8
@@ -386,8 +457,12 @@ pio=system.iobus.master[3]
 [system.t1000.fake_l2_3]
 type=IsaFake
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 fake_mem=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=2000000000
+p_state_clk_gate_min=2
 pio_addr=725849473152
 pio_latency=200
 pio_size=8
@@ -404,8 +479,12 @@ pio=system.iobus.master[4]
 [system.t1000.fake_l2_4]
 type=IsaFake
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 fake_mem=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=2000000000
+p_state_clk_gate_min=2
 pio_addr=725849473216
 pio_latency=200
 pio_size=8
@@ -422,8 +501,12 @@ pio=system.iobus.master[5]
 [system.t1000.fake_l2esr_1]
 type=IsaFake
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 fake_mem=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=2000000000
+p_state_clk_gate_min=2
 pio_addr=734439407616
 pio_latency=200
 pio_size=8
@@ -440,8 +523,12 @@ pio=system.iobus.master[6]
 [system.t1000.fake_l2esr_2]
 type=IsaFake
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 fake_mem=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=2000000000
+p_state_clk_gate_min=2
 pio_addr=734439407680
 pio_latency=200
 pio_size=8
@@ -458,8 +545,12 @@ pio=system.iobus.master[7]
 [system.t1000.fake_l2esr_3]
 type=IsaFake
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 fake_mem=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=2000000000
+p_state_clk_gate_min=2
 pio_addr=734439407744
 pio_latency=200
 pio_size=8
@@ -476,8 +567,12 @@ pio=system.iobus.master[8]
 [system.t1000.fake_l2esr_4]
 type=IsaFake
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 fake_mem=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=2000000000
+p_state_clk_gate_min=2
 pio_addr=734439407808
 pio_latency=200
 pio_size=8
@@ -494,8 +589,12 @@ pio=system.iobus.master[9]
 [system.t1000.fake_membnks]
 type=IsaFake
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 fake_mem=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=2000000000
+p_state_clk_gate_min=2
 pio_addr=648540061696
 pio_latency=200
 pio_size=16384
@@ -512,8 +611,12 @@ pio=system.iobus.master[1]
 [system.t1000.fake_ssi]
 type=IsaFake
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 fake_mem=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=2000000000
+p_state_clk_gate_min=2
 pio_addr=1095216660480
 pio_latency=200
 pio_size=268435456
@@ -538,7 +641,11 @@ port=3456
 [system.t1000.htod]
 type=DumbTOD
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=2000000000
+p_state_clk_gate_min=2
 pio_addr=1099255906296
 pio_latency=200
 system=system
@@ -548,7 +655,11 @@ pio=system.membus.master[1]
 [system.t1000.hvuart]
 type=Uart8250
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=2000000000
+p_state_clk_gate_min=2
 pio_addr=1099255955456
 pio_latency=200
 platform=system.t1000
@@ -559,7 +670,11 @@ pio=system.iobus.master[13]
 [system.t1000.iob]
 type=Iob
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=2000000000
+p_state_clk_gate_min=2
 pio_latency=2
 platform=system.t1000
 system=system
@@ -576,7 +691,11 @@ port=3456
 [system.t1000.puart0]
 type=Uart8250
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=2000000000
+p_state_clk_gate_min=2
 pio_addr=133412421632
 pio_latency=200
 platform=system.t1000
diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.json b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.json
index d144b080a87b396fc65bc435acbf383eaa049c48..00d9dd13605c38646076ba84ea4686828f62b9fa 100644 (file)
--- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.json
+++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.json
@@ -9,12 +9,16 @@
             "range": "1099243192320:1099251580927", 
             "latency": 60, 
             "name": "rom", 
+            "p_state_clk_gate_min": 2, 
             "eventq_index": 0, 
+            "p_state_clk_gate_bins": 20, 
+            "default_p_state": "UNDEFINED", 
             "clk_domain": "system.clk_domain", 
             "latency_var": 0, 
             "bandwidth": "0.000000", 
             "conf_table_reported": true, 
             "cxx_class": "SimpleMemory", 
+            "p_state_clk_gate_max": 2000000000, 
             "path": "system.rom", 
             "null": false, 
             "type": "SimpleMemory", 
@@ -37,6 +41,9 @@
                 "role": "SLAVE"
             }, 
             "name": "bridge", 
+            "p_state_clk_gate_min": 2, 
+            "p_state_clk_gate_bins": 20, 
+            "cxx_class": "Bridge", 
             "req_size": 16, 
             "clk_domain": "system.clk_domain", 
             "delay": 100, 
@@ -45,12 +52,14 @@
                 "peer": "system.iobus.slave[0]", 
                 "role": "MASTER"
             }, 
-            "cxx_class": "Bridge", 
+            "default_p_state": "UNDEFINED", 
+            "p_state_clk_gate_max": 2000000000, 
             "path": "system.bridge", 
             "resp_size": 16, 
             "type": "Bridge"
         }, 
         "iobus": {
+            "forward_latency": 1, 
             "slave": {
                 "peer": [
                     "system.bridge.master"
@@ -58,7 +67,9 @@
                 "role": "SLAVE"
             }, 
             "name": "iobus", 
-            "forward_latency": 1, 
+            "p_state_clk_gate_min": 2, 
+            "p_state_clk_gate_bins": 20, 
+            "cxx_class": "NoncoherentXBar", 
             "clk_domain": "system.clk_domain", 
             "width": 16, 
             "eventq_index": 0, 
@@ -83,7 +94,8 @@
                 "role": "MASTER"
             }, 
             "response_latency": 2, 
-            "cxx_class": "NoncoherentXBar", 
+            "default_p_state": "UNDEFINED", 
+            "p_state_clk_gate_max": 2000000000, 
             "path": "system.iobus", 
             "type": "NoncoherentXBar", 
             "use_default_range": false, 
@@ -92,110 +104,130 @@
         "t1000": {
             "htod": {
                 "name": "htod", 
+                "p_state_clk_gate_min": 2, 
                 "pio": {
                     "peer": "system.membus.master[1]", 
                     "role": "SLAVE"
                 }, 
-                "time": "Thu Jan  1 00:00:00 2009", 
+                "p_state_clk_gate_bins": 20, 
+                "cxx_class": "DumbTOD", 
                 "pio_latency": 200, 
                 "clk_domain": "system.clk_domain", 
                 "system": "system", 
                 "eventq_index": 0, 
-                "cxx_class": "DumbTOD", 
+                "time": "Thu Jan  1 00:00:00 2009", 
+                "default_p_state": "UNDEFINED", 
+                "p_state_clk_gate_max": 2000000000, 
                 "path": "system.t1000.htod", 
                 "pio_addr": 1099255906296, 
                 "type": "DumbTOD"
             }, 
             "puart0": {
                 "name": "puart0", 
+                "p_state_clk_gate_min": 2, 
                 "pio": {
                     "peer": "system.iobus.master[12]", 
                     "role": "SLAVE"
                 }, 
+                "p_state_clk_gate_bins": 20, 
+                "cxx_class": "Uart8250", 
                 "pio_latency": 200, 
                 "clk_domain": "system.clk_domain", 
                 "system": "system", 
                 "terminal": "system.t1000.pterm", 
                 "platform": "system.t1000", 
                 "eventq_index": 0, 
-                "cxx_class": "Uart8250", 
+                "default_p_state": "UNDEFINED", 
+                "p_state_clk_gate_max": 2000000000, 
                 "path": "system.t1000.puart0", 
                 "pio_addr": 133412421632, 
                 "type": "Uart8250"
             }, 
             "fake_membnks": {
-                "system": "system", 
-                "ret_data8": 255, 
-                "name": "fake_membnks", 
-                "warn_access": "", 
                 "pio": {
                     "peer": "system.iobus.master[1]", 
                     "role": "SLAVE"
                 }, 
-                "ret_bad_addr": false, 
-                "pio_latency": 200, 
-                "clk_domain": "system.clk_domain", 
-                "fake_mem": false, 
-                "pio_size": 16384, 
-                "ret_data32": 4294967295, 
-                "eventq_index": 0, 
-                "update_data": false, 
                 "ret_data64": 0, 
+                "fake_mem": false, 
+                "clk_domain": "system.clk_domain", 
                 "cxx_class": "IsaFake", 
-                "path": "system.t1000.fake_membnks", 
                 "pio_addr": 648540061696, 
+                "update_data": false, 
+                "warn_access": "", 
+                "pio_latency": 200, 
+                "system": "system", 
+                "eventq_index": 0, 
+                "default_p_state": "UNDEFINED", 
+                "p_state_clk_gate_max": 2000000000, 
                 "type": "IsaFake", 
-                "ret_data16": 65535
+                "p_state_clk_gate_min": 2, 
+                "ret_data32": 4294967295, 
+                "path": "system.t1000.fake_membnks", 
+                "ret_data16": 65535, 
+                "ret_data8": 255, 
+                "name": "fake_membnks", 
+                "ret_bad_addr": false, 
+                "pio_size": 16384, 
+                "p_state_clk_gate_bins": 20
             }, 
             "cxx_class": "T1000", 
             "fake_jbi": {
-                "system": "system", 
-                "ret_data8": 255, 
-                "name": "fake_jbi", 
-                "warn_access": "", 
                 "pio": {
                     "peer": "system.iobus.master[11]", 
                     "role": "SLAVE"
                 }, 
-                "ret_bad_addr": false, 
-                "pio_latency": 200, 
-                "clk_domain": "system.clk_domain", 
-                "fake_mem": false, 
-                "pio_size": 4294967296, 
-                "ret_data32": 4294967295, 
-                "eventq_index": 0, 
-                "update_data": false, 
                 "ret_data64": 18446744073709551615, 
+                "fake_mem": false, 
+                "clk_domain": "system.clk_domain", 
                 "cxx_class": "IsaFake", 
-                "path": "system.t1000.fake_jbi", 
                 "pio_addr": 549755813888, 
+                "update_data": false, 
+                "warn_access": "", 
+                "pio_latency": 200, 
+                "system": "system", 
+                "eventq_index": 0, 
+                "default_p_state": "UNDEFINED", 
+                "p_state_clk_gate_max": 2000000000, 
                 "type": "IsaFake", 
-                "ret_data16": 65535
+                "p_state_clk_gate_min": 2, 
+                "ret_data32": 4294967295, 
+                "path": "system.t1000.fake_jbi", 
+                "ret_data16": 65535, 
+                "ret_data8": 255, 
+                "name": "fake_jbi", 
+                "ret_bad_addr": false, 
+                "pio_size": 4294967296, 
+                "p_state_clk_gate_bins": 20
             }, 
             "intrctrl": "system.intrctrl", 
             "fake_l2esr_2": {
-                "system": "system", 
-                "ret_data8": 255, 
-                "name": "fake_l2esr_2", 
-                "warn_access": "", 
                 "pio": {
                     "peer": "system.iobus.master[7]", 
                     "role": "SLAVE"
                 }, 
-                "ret_bad_addr": false, 
-                "pio_latency": 200, 
-                "clk_domain": "system.clk_domain", 
-                "fake_mem": false, 
-                "pio_size": 8, 
-                "ret_data32": 4294967295, 
-                "eventq_index": 0, 
-                "update_data": true, 
                 "ret_data64": 0, 
+                "fake_mem": false, 
+                "clk_domain": "system.clk_domain", 
                 "cxx_class": "IsaFake", 
-                "path": "system.t1000.fake_l2esr_2", 
                 "pio_addr": 734439407680, 
+                "update_data": true, 
+                "warn_access": "", 
+                "pio_latency": 200, 
+                "system": "system", 
+                "eventq_index": 0, 
+                "default_p_state": "UNDEFINED", 
+                "p_state_clk_gate_max": 2000000000, 
                 "type": "IsaFake", 
-                "ret_data16": 65535
+                "p_state_clk_gate_min": 2, 
+                "ret_data32": 4294967295, 
+                "path": "system.t1000.fake_l2esr_2", 
+                "ret_data16": 65535, 
+                "ret_data8": 255, 
+                "name": "fake_l2esr_2", 
+                "ret_bad_addr": false, 
+                "pio_size": 8, 
+                "p_state_clk_gate_bins": 20
             }, 
             "system": "system", 
             "eventq_index": 0, 
@@ -212,100 +244,116 @@
             }, 
             "type": "T1000", 
             "fake_l2_4": {
-                "system": "system", 
-                "ret_data8": 255, 
-                "name": "fake_l2_4", 
-                "warn_access": "", 
                 "pio": {
                     "peer": "system.iobus.master[5]", 
                     "role": "SLAVE"
                 }, 
-                "ret_bad_addr": false, 
-                "pio_latency": 200, 
-                "clk_domain": "system.clk_domain", 
-                "fake_mem": false, 
-                "pio_size": 8, 
-                "ret_data32": 4294967295, 
-                "eventq_index": 0, 
-                "update_data": true, 
                 "ret_data64": 1, 
+                "fake_mem": false, 
+                "clk_domain": "system.clk_domain", 
                 "cxx_class": "IsaFake", 
-                "path": "system.t1000.fake_l2_4", 
                 "pio_addr": 725849473216, 
+                "update_data": true, 
+                "warn_access": "", 
+                "pio_latency": 200, 
+                "system": "system", 
+                "eventq_index": 0, 
+                "default_p_state": "UNDEFINED", 
+                "p_state_clk_gate_max": 2000000000, 
                 "type": "IsaFake", 
-                "ret_data16": 65535
+                "p_state_clk_gate_min": 2, 
+                "ret_data32": 4294967295, 
+                "path": "system.t1000.fake_l2_4", 
+                "ret_data16": 65535, 
+                "ret_data8": 255, 
+                "name": "fake_l2_4", 
+                "ret_bad_addr": false, 
+                "pio_size": 8, 
+                "p_state_clk_gate_bins": 20
             }, 
             "fake_l2_1": {
-                "system": "system", 
-                "ret_data8": 255, 
-                "name": "fake_l2_1", 
-                "warn_access": "", 
                 "pio": {
                     "peer": "system.iobus.master[2]", 
                     "role": "SLAVE"
                 }, 
-                "ret_bad_addr": false, 
-                "pio_latency": 200, 
-                "clk_domain": "system.clk_domain", 
-                "fake_mem": false, 
-                "pio_size": 8, 
-                "ret_data32": 4294967295, 
-                "eventq_index": 0, 
-                "update_data": true, 
                 "ret_data64": 1, 
+                "fake_mem": false, 
+                "clk_domain": "system.clk_domain", 
                 "cxx_class": "IsaFake", 
-                "path": "system.t1000.fake_l2_1", 
                 "pio_addr": 725849473024, 
+                "update_data": true, 
+                "warn_access": "", 
+                "pio_latency": 200, 
+                "system": "system", 
+                "eventq_index": 0, 
+                "default_p_state": "UNDEFINED", 
+                "p_state_clk_gate_max": 2000000000, 
                 "type": "IsaFake", 
-                "ret_data16": 65535
+                "p_state_clk_gate_min": 2, 
+                "ret_data32": 4294967295, 
+                "path": "system.t1000.fake_l2_1", 
+                "ret_data16": 65535, 
+                "ret_data8": 255, 
+                "name": "fake_l2_1", 
+                "ret_bad_addr": false, 
+                "pio_size": 8, 
+                "p_state_clk_gate_bins": 20
             }, 
             "fake_l2_2": {
-                "system": "system", 
-                "ret_data8": 255, 
-                "name": "fake_l2_2", 
-                "warn_access": "", 
                 "pio": {
                     "peer": "system.iobus.master[3]", 
                     "role": "SLAVE"
                 }, 
-                "ret_bad_addr": false, 
-                "pio_latency": 200, 
-                "clk_domain": "system.clk_domain", 
-                "fake_mem": false, 
-                "pio_size": 8, 
-                "ret_data32": 4294967295, 
-                "eventq_index": 0, 
-                "update_data": true, 
                 "ret_data64": 1, 
+                "fake_mem": false, 
+                "clk_domain": "system.clk_domain", 
                 "cxx_class": "IsaFake", 
-                "path": "system.t1000.fake_l2_2", 
                 "pio_addr": 725849473088, 
+                "update_data": true, 
+                "warn_access": "", 
+                "pio_latency": 200, 
+                "system": "system", 
+                "eventq_index": 0, 
+                "default_p_state": "UNDEFINED", 
+                "p_state_clk_gate_max": 2000000000, 
                 "type": "IsaFake", 
-                "ret_data16": 65535
+                "p_state_clk_gate_min": 2, 
+                "ret_data32": 4294967295, 
+                "path": "system.t1000.fake_l2_2", 
+                "ret_data16": 65535, 
+                "ret_data8": 255, 
+                "name": "fake_l2_2", 
+                "ret_bad_addr": false, 
+                "pio_size": 8, 
+                "p_state_clk_gate_bins": 20
             }, 
             "fake_l2_3": {
-                "system": "system", 
-                "ret_data8": 255, 
-                "name": "fake_l2_3", 
-                "warn_access": "", 
                 "pio": {
                     "peer": "system.iobus.master[4]", 
                     "role": "SLAVE"
                 }, 
-                "ret_bad_addr": false, 
-                "pio_latency": 200, 
-                "clk_domain": "system.clk_domain", 
-                "fake_mem": false, 
-                "pio_size": 8, 
-                "ret_data32": 4294967295, 
-                "eventq_index": 0, 
-                "update_data": true, 
                 "ret_data64": 1, 
+                "fake_mem": false, 
+                "clk_domain": "system.clk_domain", 
                 "cxx_class": "IsaFake", 
-                "path": "system.t1000.fake_l2_3", 
                 "pio_addr": 725849473152, 
+                "update_data": true, 
+                "warn_access": "", 
+                "pio_latency": 200, 
+                "system": "system", 
+                "eventq_index": 0, 
+                "default_p_state": "UNDEFINED", 
+                "p_state_clk_gate_max": 2000000000, 
                 "type": "IsaFake", 
-                "ret_data16": 65535
+                "p_state_clk_gate_min": 2, 
+                "ret_data32": 4294967295, 
+                "path": "system.t1000.fake_l2_3", 
+                "ret_data16": 65535, 
+                "ret_data8": 255, 
+                "name": "fake_l2_3", 
+                "ret_bad_addr": false, 
+                "pio_size": 8, 
+                "p_state_clk_gate_bins": 20
             }, 
             "pterm": {
                 "name": "pterm", 
@@ -321,171 +369,203 @@
             "path": "system.t1000", 
             "iob": {
                 "name": "iob", 
+                "p_state_clk_gate_min": 2, 
                 "pio": {
                     "peer": "system.membus.master[0]", 
                     "role": "SLAVE"
                 }, 
+                "p_state_clk_gate_bins": 20, 
+                "cxx_class": "Iob", 
                 "pio_latency": 2, 
                 "clk_domain": "system.clk_domain", 
                 "system": "system", 
                 "platform": "system.t1000", 
                 "eventq_index": 0, 
-                "cxx_class": "Iob", 
+                "default_p_state": "UNDEFINED", 
+                "p_state_clk_gate_max": 2000000000, 
                 "path": "system.t1000.iob", 
                 "type": "Iob"
             }, 
             "hvuart": {
                 "name": "hvuart", 
+                "p_state_clk_gate_min": 2, 
                 "pio": {
                     "peer": "system.iobus.master[13]", 
                     "role": "SLAVE"
                 }, 
+                "p_state_clk_gate_bins": 20, 
+                "cxx_class": "Uart8250", 
                 "pio_latency": 200, 
                 "clk_domain": "system.clk_domain", 
                 "system": "system", 
                 "terminal": "system.t1000.hterm", 
                 "platform": "system.t1000", 
                 "eventq_index": 0, 
-                "cxx_class": "Uart8250", 
+                "default_p_state": "UNDEFINED", 
+                "p_state_clk_gate_max": 2000000000, 
                 "path": "system.t1000.hvuart", 
                 "pio_addr": 1099255955456, 
                 "type": "Uart8250"
             }, 
             "name": "t1000", 
             "fake_l2esr_3": {
-                "system": "system", 
-                "ret_data8": 255, 
-                "name": "fake_l2esr_3", 
-                "warn_access": "", 
                 "pio": {
                     "peer": "system.iobus.master[8]", 
                     "role": "SLAVE"
                 }, 
-                "ret_bad_addr": false, 
-                "pio_latency": 200, 
-                "clk_domain": "system.clk_domain", 
-                "fake_mem": false, 
-                "pio_size": 8, 
-                "ret_data32": 4294967295, 
-                "eventq_index": 0, 
-                "update_data": true, 
                 "ret_data64": 0, 
+                "fake_mem": false, 
+                "clk_domain": "system.clk_domain", 
                 "cxx_class": "IsaFake", 
-                "path": "system.t1000.fake_l2esr_3", 
                 "pio_addr": 734439407744, 
+                "update_data": true, 
+                "warn_access": "", 
+                "pio_latency": 200, 
+                "system": "system", 
+                "eventq_index": 0, 
+                "default_p_state": "UNDEFINED", 
+                "p_state_clk_gate_max": 2000000000, 
                 "type": "IsaFake", 
-                "ret_data16": 65535
+                "p_state_clk_gate_min": 2, 
+                "ret_data32": 4294967295, 
+                "path": "system.t1000.fake_l2esr_3", 
+                "ret_data16": 65535, 
+                "ret_data8": 255, 
+                "name": "fake_l2esr_3", 
+                "ret_bad_addr": false, 
+                "pio_size": 8, 
+                "p_state_clk_gate_bins": 20
             }, 
             "fake_ssi": {
-                "system": "system", 
-                "ret_data8": 255, 
-                "name": "fake_ssi", 
-                "warn_access": "", 
                 "pio": {
                     "peer": "system.iobus.master[10]", 
                     "role": "SLAVE"
                 }, 
-                "ret_bad_addr": false, 
-                "pio_latency": 200, 
-                "clk_domain": "system.clk_domain", 
-                "fake_mem": false, 
-                "pio_size": 268435456, 
-                "ret_data32": 4294967295, 
-                "eventq_index": 0, 
-                "update_data": false, 
                 "ret_data64": 18446744073709551615, 
+                "fake_mem": false, 
+                "clk_domain": "system.clk_domain", 
                 "cxx_class": "IsaFake", 
-                "path": "system.t1000.fake_ssi", 
                 "pio_addr": 1095216660480, 
+                "update_data": false, 
+                "warn_access": "", 
+                "pio_latency": 200, 
+                "system": "system", 
+                "eventq_index": 0, 
+                "default_p_state": "UNDEFINED", 
+                "p_state_clk_gate_max": 2000000000, 
                 "type": "IsaFake", 
-                "ret_data16": 65535
+                "p_state_clk_gate_min": 2, 
+                "ret_data32": 4294967295, 
+                "path": "system.t1000.fake_ssi", 
+                "ret_data16": 65535, 
+                "ret_data8": 255, 
+                "name": "fake_ssi", 
+                "ret_bad_addr": false, 
+                "pio_size": 268435456, 
+                "p_state_clk_gate_bins": 20
             }, 
             "fake_l2esr_1": {
-                "system": "system", 
-                "ret_data8": 255, 
-                "name": "fake_l2esr_1", 
-                "warn_access": "", 
                 "pio": {
                     "peer": "system.iobus.master[6]", 
                     "role": "SLAVE"
                 }, 
-                "ret_bad_addr": false, 
-                "pio_latency": 200, 
-                "clk_domain": "system.clk_domain", 
-                "fake_mem": false, 
-                "pio_size": 8, 
-                "ret_data32": 4294967295, 
-                "eventq_index": 0, 
-                "update_data": true, 
                 "ret_data64": 0, 
+                "fake_mem": false, 
+                "clk_domain": "system.clk_domain", 
                 "cxx_class": "IsaFake", 
-                "path": "system.t1000.fake_l2esr_1", 
                 "pio_addr": 734439407616, 
+                "update_data": true, 
+                "warn_access": "", 
+                "pio_latency": 200, 
+                "system": "system", 
+                "eventq_index": 0, 
+                "default_p_state": "UNDEFINED", 
+                "p_state_clk_gate_max": 2000000000, 
                 "type": "IsaFake", 
-                "ret_data16": 65535
+                "p_state_clk_gate_min": 2, 
+                "ret_data32": 4294967295, 
+                "path": "system.t1000.fake_l2esr_1", 
+                "ret_data16": 65535, 
+                "ret_data8": 255, 
+                "name": "fake_l2esr_1", 
+                "ret_bad_addr": false, 
+                "pio_size": 8, 
+                "p_state_clk_gate_bins": 20
             }, 
             "fake_l2esr_4": {
-                "system": "system", 
-                "ret_data8": 255, 
-                "name": "fake_l2esr_4", 
-                "warn_access": "", 
                 "pio": {
                     "peer": "system.iobus.master[9]", 
                     "role": "SLAVE"
                 }, 
-                "ret_bad_addr": false, 
-                "pio_latency": 200, 
-                "clk_domain": "system.clk_domain", 
-                "fake_mem": false, 
-                "pio_size": 8, 
-                "ret_data32": 4294967295, 
-                "eventq_index": 0, 
-                "update_data": true, 
                 "ret_data64": 0, 
+                "fake_mem": false, 
+                "clk_domain": "system.clk_domain", 
                 "cxx_class": "IsaFake", 
-                "path": "system.t1000.fake_l2esr_4", 
                 "pio_addr": 734439407808, 
+                "update_data": true, 
+                "warn_access": "", 
+                "pio_latency": 200, 
+                "system": "system", 
+                "eventq_index": 0, 
+                "default_p_state": "UNDEFINED", 
+                "p_state_clk_gate_max": 2000000000, 
                 "type": "IsaFake", 
-                "ret_data16": 65535
+                "p_state_clk_gate_min": 2, 
+                "ret_data32": 4294967295, 
+                "path": "system.t1000.fake_l2esr_4", 
+                "ret_data16": 65535, 
+                "ret_data8": 255, 
+                "name": "fake_l2esr_4", 
+                "ret_bad_addr": false, 
+                "pio_size": 8, 
+                "p_state_clk_gate_bins": 20
             }, 
             "fake_clk": {
-                "system": "system", 
-                "ret_data8": 255, 
-                "name": "fake_clk", 
-                "warn_access": "", 
                 "pio": {
                     "peer": "system.iobus.master[0]", 
                     "role": "SLAVE"
                 }, 
-                "ret_bad_addr": false, 
-                "pio_latency": 200, 
-                "clk_domain": "system.clk_domain", 
-                "fake_mem": false, 
-                "pio_size": 4294967296, 
-                "ret_data32": 4294967295, 
-                "eventq_index": 0, 
-                "update_data": false, 
                 "ret_data64": 18446744073709551615, 
+                "fake_mem": false, 
+                "clk_domain": "system.clk_domain", 
                 "cxx_class": "IsaFake", 
-                "path": "system.t1000.fake_clk", 
                 "pio_addr": 644245094400, 
+                "update_data": false, 
+                "warn_access": "", 
+                "pio_latency": 200, 
+                "system": "system", 
+                "eventq_index": 0, 
+                "default_p_state": "UNDEFINED", 
+                "p_state_clk_gate_max": 2000000000, 
                 "type": "IsaFake", 
-                "ret_data16": 65535
+                "p_state_clk_gate_min": 2, 
+                "ret_data32": 4294967295, 
+                "path": "system.t1000.fake_clk", 
+                "ret_data16": 65535, 
+                "ret_data8": 255, 
+                "name": "fake_clk", 
+                "ret_bad_addr": false, 
+                "pio_size": 4294967296, 
+                "p_state_clk_gate_bins": 20
             }
         }, 
         "partition_desc_addr": 133445976064, 
         "symbolfile": "", 
-        "readfile": "/z/stever/hg/gem5/tests/halt.sh", 
+        "readfile": "/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh", 
+        "thermal_model": null, 
         "hypervisor_addr": 1099243257856, 
         "mem_ranges": [
             "1048576:68157439", 
             "2147483648:2415919103"
         ], 
         "cxx_class": "SparcSystem", 
+        "work_begin_cpu_id_exit": -1, 
         "load_offset": 0, 
-        "reset_bin": "/dist/m5/system/binaries/reset_new.bin", 
-        "openboot_addr": 1099243716608, 
+        "reset_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/reset_new.bin", 
         "work_end_ckpt_count": 0, 
+        "work_begin_exit_count": 0, 
+        "openboot_addr": 1099243716608, 
+        "p_state_clk_gate_min": 2, 
         "nvram_addr": 133429198848, 
         "memories": [
             "system.hypervisor_desc", 
@@ -500,12 +580,16 @@
             "range": "133445976064:133445984255", 
             "latency": 60, 
             "name": "partition_desc", 
+            "p_state_clk_gate_min": 2, 
             "eventq_index": 0, 
+            "p_state_clk_gate_bins": 20, 
+            "default_p_state": "UNDEFINED", 
             "clk_domain": "system.clk_domain", 
             "latency_var": 0, 
             "bandwidth": "0.000000", 
             "conf_table_reported": true, 
             "cxx_class": "SimpleMemory", 
+            "p_state_clk_gate_max": 2000000000, 
             "path": "system.partition_desc", 
             "null": false, 
             "type": "SimpleMemory", 
@@ -532,12 +616,16 @@
             "range": "133446500352:133446508543", 
             "latency": 60, 
             "name": "hypervisor_desc", 
+            "p_state_clk_gate_min": 2, 
             "eventq_index": 0, 
+            "p_state_clk_gate_bins": 20, 
+            "default_p_state": "UNDEFINED", 
             "clk_domain": "system.clk_domain", 
             "latency_var": 0, 
             "bandwidth": "0.000000", 
             "conf_table_reported": true, 
             "cxx_class": "SimpleMemory", 
+            "p_state_clk_gate_max": 2000000000, 
             "path": "system.hypervisor_desc", 
             "null": false, 
             "type": "SimpleMemory", 
@@ -548,49 +636,44 @@
             "in_addr_map": true
         }, 
         "membus": {
-            "default": {
-                "peer": "system.membus.badaddr_responder.pio", 
-                "role": "MASTER"
-            }, 
-            "slave": {
-                "peer": [
-                    "system.system_port", 
-                    "system.cpu.icache_port", 
-                    "system.cpu.dcache_port"
-                ], 
-                "role": "SLAVE"
-            }, 
-            "name": "membus", 
+            "point_of_coherency": true, 
+            "system": "system", 
+            "response_latency": 2, 
+            "cxx_class": "CoherentXBar", 
             "badaddr_responder": {
-                "system": "system", 
-                "ret_data8": 255, 
-                "name": "badaddr_responder", 
-                "warn_access": "", 
                 "pio": {
                     "peer": "system.membus.default", 
                     "role": "SLAVE"
                 }, 
-                "ret_bad_addr": true, 
-                "pio_latency": 200, 
-                "clk_domain": "system.clk_domain", 
-                "fake_mem": false, 
-                "pio_size": 8, 
-                "ret_data32": 4294967295, 
-                "eventq_index": 0, 
-                "update_data": false, 
                 "ret_data64": 18446744073709551615, 
+                "fake_mem": false, 
+                "clk_domain": "system.clk_domain", 
                 "cxx_class": "IsaFake", 
-                "path": "system.membus.badaddr_responder", 
                 "pio_addr": 0, 
+                "update_data": false, 
+                "warn_access": "", 
+                "pio_latency": 200, 
+                "system": "system", 
+                "eventq_index": 0, 
+                "default_p_state": "UNDEFINED", 
+                "p_state_clk_gate_max": 2000000000, 
                 "type": "IsaFake", 
-                "ret_data16": 65535
+                "p_state_clk_gate_min": 2, 
+                "ret_data32": 4294967295, 
+                "path": "system.membus.badaddr_responder", 
+                "ret_data16": 65535, 
+                "ret_data8": 255, 
+                "name": "badaddr_responder", 
+                "ret_bad_addr": true, 
+                "pio_size": 8, 
+                "p_state_clk_gate_bins": 20
             }, 
-            "snoop_filter": null, 
             "forward_latency": 4, 
             "clk_domain": "system.clk_domain", 
-            "system": "system", 
             "width": 16, 
             "eventq_index": 0, 
+            "default_p_state": "UNDEFINED", 
+            "p_state_clk_gate_max": 2000000000, 
             "master": {
                 "peer": [
                     "system.t1000.iob.pio", 
@@ -605,24 +688,42 @@
                 ], 
                 "role": "MASTER"
             }, 
-            "response_latency": 2, 
-            "cxx_class": "CoherentXBar", 
+            "type": "CoherentXBar", 
+            "frontend_latency": 3, 
+            "slave": {
+                "peer": [
+                    "system.system_port", 
+                    "system.cpu.icache_port", 
+                    "system.cpu.dcache_port"
+                ], 
+                "role": "SLAVE"
+            }, 
+            "p_state_clk_gate_min": 2, 
+            "snoop_filter": null, 
             "path": "system.membus", 
             "snoop_response_latency": 4, 
-            "type": "CoherentXBar", 
-            "use_default_range": false, 
-            "frontend_latency": 3
+            "name": "membus", 
+            "default": {
+                "peer": "system.membus.badaddr_responder.pio", 
+                "role": "MASTER"
+            }, 
+            "p_state_clk_gate_bins": 20, 
+            "use_default_range": false
         }, 
         "nvram": {
             "range": "133429198848:133429207039", 
             "latency": 60, 
             "name": "nvram", 
+            "p_state_clk_gate_min": 2, 
             "eventq_index": 0, 
+            "p_state_clk_gate_bins": 20, 
+            "default_p_state": "UNDEFINED", 
             "clk_domain": "system.clk_domain", 
             "latency_var": 0, 
             "bandwidth": "0.000000", 
             "conf_table_reported": true, 
             "cxx_class": "SimpleMemory", 
+            "p_state_clk_gate_max": 2000000000, 
             "path": "system.nvram", 
             "null": false, 
             "type": "SimpleMemory", 
@@ -633,7 +734,8 @@
             "in_addr_map": true
         }, 
         "eventq_index": 0, 
-        "work_begin_cpu_id_exit": -1, 
+        "default_p_state": "UNDEFINED", 
+        "p_state_clk_gate_max": 2000000000, 
         "dvfs_handler": {
             "enable": false, 
             "name": "dvfs_handler", 
@@ -646,8 +748,8 @@
             "type": "DVFSHandler"
         }, 
         "work_end_exit_count": 0, 
-        "hypervisor_desc_bin": "/dist/m5/system/binaries/1up-hv.bin", 
-        "openboot_bin": "/dist/m5/system/binaries/openboot_new.bin", 
+        "hypervisor_desc_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/1up-hv.bin", 
+        "openboot_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/openboot_new.bin", 
         "voltage_domain": {
             "name": "voltage_domain", 
             "eventq_index": 0, 
@@ -669,12 +771,16 @@
                 "range": "1048576:68157439", 
                 "latency": 60, 
                 "name": "physmem0", 
+                "p_state_clk_gate_min": 2, 
                 "eventq_index": 0, 
+                "p_state_clk_gate_bins": 20, 
+                "default_p_state": "UNDEFINED", 
                 "clk_domain": "system.clk_domain", 
                 "latency_var": 0, 
                 "bandwidth": "0.000000", 
                 "conf_table_reported": true, 
                 "cxx_class": "SimpleMemory", 
+                "p_state_clk_gate_max": 2000000000, 
                 "path": "system.physmem0", 
                 "null": false, 
                 "type": "SimpleMemory", 
@@ -688,12 +794,16 @@
                 "range": "2147483648:2415919103", 
                 "latency": 60, 
                 "name": "physmem1", 
+                "p_state_clk_gate_min": 2, 
                 "eventq_index": 0, 
+                "p_state_clk_gate_bins": 20, 
+                "default_p_state": "UNDEFINED", 
                 "clk_domain": "system.clk_domain", 
                 "latency_var": 0, 
                 "bandwidth": "0.000000", 
                 "conf_table_reported": true, 
                 "cxx_class": "SimpleMemory", 
+                "p_state_clk_gate_max": 2000000000, 
                 "path": "system.physmem1", 
                 "null": false, 
                 "type": "SimpleMemory", 
@@ -705,9 +815,9 @@
             }
         ], 
         "work_cpus_ckpt_count": 0, 
-        "work_begin_exit_count": 0, 
+        "thermal_components": [], 
         "path": "system", 
-        "hypervisor_bin": "/dist/m5/system/binaries/q_new.bin", 
+        "hypervisor_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/q_new.bin", 
         "cpu_clk_domain": {
             "name": "cpu_clk_domain", 
             "clock": [
@@ -721,12 +831,12 @@
             "type": "SrcClockDomain", 
             "domain_id": -1
         }, 
-        "nvram_bin": "/dist/m5/system/binaries/nvram1", 
+        "nvram_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/nvram1", 
         "mem_mode": "atomic", 
         "name": "system", 
         "init_param": 0, 
         "type": "SparcSystem", 
-        "partition_desc_bin": "/dist/m5/system/binaries/1up-md.bin", 
+        "partition_desc_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/1up-md.bin", 
         "load_addr_mask": 1099511627775, 
         "cpu": {
             "do_statistics_insts": true, 
@@ -751,6 +861,8 @@
             "width": 1, 
             "checker": null, 
             "eventq_index": 0, 
+            "default_p_state": "UNDEFINED", 
+            "p_state_clk_gate_max": 2000000000, 
             "do_quiesce": true, 
             "type": "AtomicSimpleCPU", 
             "fastmem": false, 
@@ -759,6 +871,8 @@
                 "peer": "system.membus.slave[1]", 
                 "role": "MASTER"
             }, 
+            "p_state_clk_gate_bins": 20, 
+            "p_state_clk_gate_min": 2, 
             "interrupts": [
                 {
                     "eventq_index": 0, 
@@ -819,10 +933,12 @@
         }, 
         "disk0": {
             "name": "disk0", 
+            "p_state_clk_gate_min": 2, 
             "pio": {
                 "peer": "system.iobus.master[14]", 
                 "role": "SLAVE"
             }, 
+            "p_state_clk_gate_bins": 20, 
             "image": {
                 "read_only": false, 
                 "name": "image", 
@@ -834,7 +950,7 @@
                     "eventq_index": 0, 
                     "cxx_class": "RawDiskImage", 
                     "path": "system.disk0.image.child", 
-                    "image_file": "/dist/m5/system/disks/disk.s10hw2", 
+                    "image_file": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/disk.s10hw2", 
                     "type": "RawDiskImage"
                 }, 
                 "path": "system.disk0.image", 
@@ -842,17 +958,20 @@
                 "type": "CowDiskImage", 
                 "table_size": 65536
             }, 
+            "cxx_class": "MmDisk", 
             "pio_latency": 200, 
             "clk_domain": "system.clk_domain", 
             "system": "system", 
             "eventq_index": 0, 
-            "cxx_class": "MmDisk", 
+            "default_p_state": "UNDEFINED", 
+            "p_state_clk_gate_max": 2000000000, 
             "path": "system.disk0", 
             "pio_addr": 134217728000, 
             "type": "MmDisk"
         }, 
         "multi_thread": false, 
         "reset_addr": 1099243192320, 
+        "p_state_clk_gate_bins": 20, 
         "hypervisor_desc_addr": 133446500352, 
         "num_work_ids": 16, 
         "work_item_id": -1, 
diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
index b6d9eae8b25deef1cd7eae0f2a5d11c640439d71..49b0314424cf30aa1ff8755ecfd755ce4a4864e7 100755 (executable)
--- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
+++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
@@ -1,10 +1,12 @@
+Redirecting stdout to build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic/simout
+Redirecting stderr to build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 17 2016 20:30:24
-gem5 started Jan 17 2016 20:30:38
-gem5 executing on zizzer, pid 47389
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re /z/stever/hg/gem5/tests/run.py build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic
+gem5 compiled Apr  4 2017 00:40:32
+gem5 started Apr  4 2017 00:40:43
+gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 88259
+command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic
 
 Global frequency set at 2000000000 ticks per second
 info: No kernel set for full system simulation. Assuming you know what you're doing
diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
index e3be24d87ec3e74de51a80e0f2bee6b186b17ee1..a8aedcdf7a0ec03365cf67d56a871c1769e1d538 100644 (file)
--- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
+++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
@@ -4,15 +4,49 @@ sim_seconds                                  2.233778                       # Nu
 sim_ticks                                  4467555024                       # Number of ticks simulated
 final_tick                                 4467555024                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   2000000000                       # Frequency of simulated ticks
-host_inst_rate                                1658224                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1658876                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                3324623                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 518260                       # Number of bytes of host memory used
-host_seconds                                  1343.78                       # Real time elapsed on the host
+host_inst_rate                                3235443                       # Simulator instruction rate (inst/s)
+host_op_rate                                  3236715                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                6486837                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 551372                       # Number of bytes of host memory used
+host_seconds                                   688.71                       # Real time elapsed on the host
 sim_insts                                  2228284650                       # Number of instructions simulated
 sim_ops                                    2229160714                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                             2                       # Clock period in ticks
+system.hypervisor_desc.numPwrStateTransitions            0                       # Number of power state transitions
+system.hypervisor_desc.pwrStateClkGateDist::samples            0                       # Distribution of time spent in the clock gated state
+system.hypervisor_desc.pwrStateClkGateDist::mean          nan                       # Distribution of time spent in the clock gated state
+system.hypervisor_desc.pwrStateClkGateDist::stdev          nan                       # Distribution of time spent in the clock gated state
+system.hypervisor_desc.pwrStateClkGateDist::underflows            0                       # Distribution of time spent in the clock gated state
+system.hypervisor_desc.pwrStateClkGateDist::2-1e+08            0                       # Distribution of time spent in the clock gated state
+system.hypervisor_desc.pwrStateClkGateDist::1e+08-2e+08            0                       # Distribution of time spent in the clock gated state
+system.hypervisor_desc.pwrStateClkGateDist::2e+08-3e+08            0                       # Distribution of time spent in the clock gated state
+system.hypervisor_desc.pwrStateClkGateDist::3e+08-4e+08            0                       # Distribution of time spent in the clock gated state
+system.hypervisor_desc.pwrStateClkGateDist::4e+08-5e+08            0                       # Distribution of time spent in the clock gated state
+system.hypervisor_desc.pwrStateClkGateDist::5e+08-6e+08            0                       # Distribution of time spent in the clock gated state
+system.hypervisor_desc.pwrStateClkGateDist::6e+08-7e+08            0                       # Distribution of time spent in the clock gated state
+system.hypervisor_desc.pwrStateClkGateDist::7e+08-8e+08            0                       # Distribution of time spent in the clock gated state
+system.hypervisor_desc.pwrStateClkGateDist::8e+08-9e+08            0                       # Distribution of time spent in the clock gated state
+system.hypervisor_desc.pwrStateClkGateDist::9e+08-1e+09            0                       # Distribution of time spent in the clock gated state
+system.hypervisor_desc.pwrStateClkGateDist::1e+09-1.1e+09            0                       # Distribution of time spent in the clock gated state
+system.hypervisor_desc.pwrStateClkGateDist::1.1e+09-1.2e+09            0                       # Distribution of time spent in the clock gated state
+system.hypervisor_desc.pwrStateClkGateDist::1.2e+09-1.3e+09            0                       # Distribution of time spent in the clock gated state
+system.hypervisor_desc.pwrStateClkGateDist::1.3e+09-1.4e+09            0                       # Distribution of time spent in the clock gated state
+system.hypervisor_desc.pwrStateClkGateDist::1.4e+09-1.5e+09            0                       # Distribution of time spent in the clock gated state
+system.hypervisor_desc.pwrStateClkGateDist::1.5e+09-1.6e+09            0                       # Distribution of time spent in the clock gated state
+system.hypervisor_desc.pwrStateClkGateDist::1.6e+09-1.7e+09            0                       # Distribution of time spent in the clock gated state
+system.hypervisor_desc.pwrStateClkGateDist::1.7e+09-1.8e+09            0                       # Distribution of time spent in the clock gated state
+system.hypervisor_desc.pwrStateClkGateDist::1.8e+09-1.9e+09            0                       # Distribution of time spent in the clock gated state
+system.hypervisor_desc.pwrStateClkGateDist::1.9e+09-2e+09            0                       # Distribution of time spent in the clock gated state
+system.hypervisor_desc.pwrStateClkGateDist::overflows            0                       # Distribution of time spent in the clock gated state
+system.hypervisor_desc.pwrStateClkGateDist::min_value            0                       # Distribution of time spent in the clock gated state
+system.hypervisor_desc.pwrStateClkGateDist::max_value            0                       # Distribution of time spent in the clock gated state
+system.hypervisor_desc.pwrStateClkGateDist::total            0                       # Distribution of time spent in the clock gated state
+system.hypervisor_desc.pwrStateResidencyTicks::UNDEFINED   4467555024                       # Cumulative time (in ticks) in various power states
+system.hypervisor_desc.pwrStateResidencyTicks::ON            0                       # Cumulative time (in ticks) in various power states
+system.hypervisor_desc.pwrStateResidencyTicks::CLK_GATED            0                       # Cumulative time (in ticks) in various power states
+system.hypervisor_desc.pwrStateResidencyTicks::SRAM_RETENTION            0                       # Cumulative time (in ticks) in various power states
+system.hypervisor_desc.pwrStateResidencyTicks::OFF            0                       # Cumulative time (in ticks) in various power states
 system.hypervisor_desc.bytes_read::cpu.data        16792                       # Number of bytes read from this memory
 system.hypervisor_desc.bytes_read::total        16792                       # Number of bytes read from this memory
 system.hypervisor_desc.num_reads::cpu.data         9024                       # Number of read requests responded to by this memory
@@ -21,6 +55,40 @@ system.hypervisor_desc.bw_read::cpu.data         7517                       # To
 system.hypervisor_desc.bw_read::total            7517                       # Total read bandwidth from this memory (bytes/s)
 system.hypervisor_desc.bw_total::cpu.data         7517                       # Total bandwidth to/from this memory (bytes/s)
 system.hypervisor_desc.bw_total::total           7517                       # Total bandwidth to/from this memory (bytes/s)
+system.nvram.numPwrStateTransitions                 0                       # Number of power state transitions
+system.nvram.pwrStateClkGateDist::samples            0                       # Distribution of time spent in the clock gated state
+system.nvram.pwrStateClkGateDist::mean            nan                       # Distribution of time spent in the clock gated state
+system.nvram.pwrStateClkGateDist::stdev           nan                       # Distribution of time spent in the clock gated state
+system.nvram.pwrStateClkGateDist::underflows            0                       # Distribution of time spent in the clock gated state
+system.nvram.pwrStateClkGateDist::2-1e+08            0                       # Distribution of time spent in the clock gated state
+system.nvram.pwrStateClkGateDist::1e+08-2e+08            0                       # Distribution of time spent in the clock gated state
+system.nvram.pwrStateClkGateDist::2e+08-3e+08            0                       # Distribution of time spent in the clock gated state
+system.nvram.pwrStateClkGateDist::3e+08-4e+08            0                       # Distribution of time spent in the clock gated state
+system.nvram.pwrStateClkGateDist::4e+08-5e+08            0                       # Distribution of time spent in the clock gated state
+system.nvram.pwrStateClkGateDist::5e+08-6e+08            0                       # Distribution of time spent in the clock gated state
+system.nvram.pwrStateClkGateDist::6e+08-7e+08            0                       # Distribution of time spent in the clock gated state
+system.nvram.pwrStateClkGateDist::7e+08-8e+08            0                       # Distribution of time spent in the clock gated state
+system.nvram.pwrStateClkGateDist::8e+08-9e+08            0                       # Distribution of time spent in the clock gated state
+system.nvram.pwrStateClkGateDist::9e+08-1e+09            0                       # Distribution of time spent in the clock gated state
+system.nvram.pwrStateClkGateDist::1e+09-1.1e+09            0                       # Distribution of time spent in the clock gated state
+system.nvram.pwrStateClkGateDist::1.1e+09-1.2e+09            0                       # Distribution of time spent in the clock gated state
+system.nvram.pwrStateClkGateDist::1.2e+09-1.3e+09            0                       # Distribution of time spent in the clock gated state
+system.nvram.pwrStateClkGateDist::1.3e+09-1.4e+09            0                       # Distribution of time spent in the clock gated state
+system.nvram.pwrStateClkGateDist::1.4e+09-1.5e+09            0                       # Distribution of time spent in the clock gated state
+system.nvram.pwrStateClkGateDist::1.5e+09-1.6e+09            0                       # Distribution of time spent in the clock gated state
+system.nvram.pwrStateClkGateDist::1.6e+09-1.7e+09            0                       # Distribution of time spent in the clock gated state
+system.nvram.pwrStateClkGateDist::1.7e+09-1.8e+09            0                       # Distribution of time spent in the clock gated state
+system.nvram.pwrStateClkGateDist::1.8e+09-1.9e+09            0                       # Distribution of time spent in the clock gated state
+system.nvram.pwrStateClkGateDist::1.9e+09-2e+09            0                       # Distribution of time spent in the clock gated state
+system.nvram.pwrStateClkGateDist::overflows            0                       # Distribution of time spent in the clock gated state
+system.nvram.pwrStateClkGateDist::min_value            0                       # Distribution of time spent in the clock gated state
+system.nvram.pwrStateClkGateDist::max_value            0                       # Distribution of time spent in the clock gated state
+system.nvram.pwrStateClkGateDist::total             0                       # Distribution of time spent in the clock gated state
+system.nvram.pwrStateResidencyTicks::UNDEFINED   4467555024                       # Cumulative time (in ticks) in various power states
+system.nvram.pwrStateResidencyTicks::ON             0                       # Cumulative time (in ticks) in various power states
+system.nvram.pwrStateResidencyTicks::CLK_GATED            0                       # Cumulative time (in ticks) in various power states
+system.nvram.pwrStateResidencyTicks::SRAM_RETENTION            0                       # Cumulative time (in ticks) in various power states
+system.nvram.pwrStateResidencyTicks::OFF            0                       # Cumulative time (in ticks) in various power states
 system.nvram.bytes_read::cpu.data                 284                       # Number of bytes read from this memory
 system.nvram.bytes_read::total                    284                       # Number of bytes read from this memory
 system.nvram.bytes_written::cpu.data               92                       # Number of bytes written to this memory
@@ -35,6 +103,40 @@ system.nvram.bw_write::cpu.data                    41                       # Wr
 system.nvram.bw_write::total                       41                       # Write bandwidth from this memory (bytes/s)
 system.nvram.bw_total::cpu.data                   168                       # Total bandwidth to/from this memory (bytes/s)
 system.nvram.bw_total::total                      168                       # Total bandwidth to/from this memory (bytes/s)
+system.partition_desc.numPwrStateTransitions            0                       # Number of power state transitions
+system.partition_desc.pwrStateClkGateDist::samples            0                       # Distribution of time spent in the clock gated state
+system.partition_desc.pwrStateClkGateDist::mean          nan                       # Distribution of time spent in the clock gated state
+system.partition_desc.pwrStateClkGateDist::stdev          nan                       # Distribution of time spent in the clock gated state
+system.partition_desc.pwrStateClkGateDist::underflows            0                       # Distribution of time spent in the clock gated state
+system.partition_desc.pwrStateClkGateDist::2-1e+08            0                       # Distribution of time spent in the clock gated state
+system.partition_desc.pwrStateClkGateDist::1e+08-2e+08            0                       # Distribution of time spent in the clock gated state
+system.partition_desc.pwrStateClkGateDist::2e+08-3e+08            0                       # Distribution of time spent in the clock gated state
+system.partition_desc.pwrStateClkGateDist::3e+08-4e+08            0                       # Distribution of time spent in the clock gated state
+system.partition_desc.pwrStateClkGateDist::4e+08-5e+08            0                       # Distribution of time spent in the clock gated state
+system.partition_desc.pwrStateClkGateDist::5e+08-6e+08            0                       # Distribution of time spent in the clock gated state
+system.partition_desc.pwrStateClkGateDist::6e+08-7e+08            0                       # Distribution of time spent in the clock gated state
+system.partition_desc.pwrStateClkGateDist::7e+08-8e+08            0                       # Distribution of time spent in the clock gated state
+system.partition_desc.pwrStateClkGateDist::8e+08-9e+08            0                       # Distribution of time spent in the clock gated state
+system.partition_desc.pwrStateClkGateDist::9e+08-1e+09            0                       # Distribution of time spent in the clock gated state
+system.partition_desc.pwrStateClkGateDist::1e+09-1.1e+09            0                       # Distribution of time spent in the clock gated state
+system.partition_desc.pwrStateClkGateDist::1.1e+09-1.2e+09            0                       # Distribution of time spent in the clock gated state
+system.partition_desc.pwrStateClkGateDist::1.2e+09-1.3e+09            0                       # Distribution of time spent in the clock gated state
+system.partition_desc.pwrStateClkGateDist::1.3e+09-1.4e+09            0                       # Distribution of time spent in the clock gated state
+system.partition_desc.pwrStateClkGateDist::1.4e+09-1.5e+09            0                       # Distribution of time spent in the clock gated state
+system.partition_desc.pwrStateClkGateDist::1.5e+09-1.6e+09            0                       # Distribution of time spent in the clock gated state
+system.partition_desc.pwrStateClkGateDist::1.6e+09-1.7e+09            0                       # Distribution of time spent in the clock gated state
+system.partition_desc.pwrStateClkGateDist::1.7e+09-1.8e+09            0                       # Distribution of time spent in the clock gated state
+system.partition_desc.pwrStateClkGateDist::1.8e+09-1.9e+09            0                       # Distribution of time spent in the clock gated state
+system.partition_desc.pwrStateClkGateDist::1.9e+09-2e+09            0                       # Distribution of time spent in the clock gated state
+system.partition_desc.pwrStateClkGateDist::overflows            0                       # Distribution of time spent in the clock gated state
+system.partition_desc.pwrStateClkGateDist::min_value            0                       # Distribution of time spent in the clock gated state
+system.partition_desc.pwrStateClkGateDist::max_value            0                       # Distribution of time spent in the clock gated state
+system.partition_desc.pwrStateClkGateDist::total            0                       # Distribution of time spent in the clock gated state
+system.partition_desc.pwrStateResidencyTicks::UNDEFINED   4467555024                       # Cumulative time (in ticks) in various power states
+system.partition_desc.pwrStateResidencyTicks::ON            0                       # Cumulative time (in ticks) in various power states
+system.partition_desc.pwrStateResidencyTicks::CLK_GATED            0                       # Cumulative time (in ticks) in various power states
+system.partition_desc.pwrStateResidencyTicks::SRAM_RETENTION            0                       # Cumulative time (in ticks) in various power states
+system.partition_desc.pwrStateResidencyTicks::OFF            0                       # Cumulative time (in ticks) in various power states
 system.partition_desc.bytes_read::cpu.data         4846                       # Number of bytes read from this memory
 system.partition_desc.bytes_read::total          4846                       # Number of bytes read from this memory
 system.partition_desc.num_reads::cpu.data          608                       # Number of read requests responded to by this memory
@@ -43,6 +145,40 @@ system.partition_desc.bw_read::cpu.data          2169                       # To
 system.partition_desc.bw_read::total             2169                       # Total read bandwidth from this memory (bytes/s)
 system.partition_desc.bw_total::cpu.data         2169                       # Total bandwidth to/from this memory (bytes/s)
 system.partition_desc.bw_total::total            2169                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem0.numPwrStateTransitions              0                       # Number of power state transitions
+system.physmem0.pwrStateClkGateDist::samples            0                       # Distribution of time spent in the clock gated state
+system.physmem0.pwrStateClkGateDist::mean          nan                       # Distribution of time spent in the clock gated state
+system.physmem0.pwrStateClkGateDist::stdev          nan                       # Distribution of time spent in the clock gated state
+system.physmem0.pwrStateClkGateDist::underflows            0                       # Distribution of time spent in the clock gated state
+system.physmem0.pwrStateClkGateDist::2-1e+08            0                       # Distribution of time spent in the clock gated state
+system.physmem0.pwrStateClkGateDist::1e+08-2e+08            0                       # Distribution of time spent in the clock gated state
+system.physmem0.pwrStateClkGateDist::2e+08-3e+08            0                       # Distribution of time spent in the clock gated state
+system.physmem0.pwrStateClkGateDist::3e+08-4e+08            0                       # Distribution of time spent in the clock gated state
+system.physmem0.pwrStateClkGateDist::4e+08-5e+08            0                       # Distribution of time spent in the clock gated state
+system.physmem0.pwrStateClkGateDist::5e+08-6e+08            0                       # Distribution of time spent in the clock gated state
+system.physmem0.pwrStateClkGateDist::6e+08-7e+08            0                       # Distribution of time spent in the clock gated state
+system.physmem0.pwrStateClkGateDist::7e+08-8e+08            0                       # Distribution of time spent in the clock gated state
+system.physmem0.pwrStateClkGateDist::8e+08-9e+08            0                       # Distribution of time spent in the clock gated state
+system.physmem0.pwrStateClkGateDist::9e+08-1e+09            0                       # Distribution of time spent in the clock gated state
+system.physmem0.pwrStateClkGateDist::1e+09-1.1e+09            0                       # Distribution of time spent in the clock gated state
+system.physmem0.pwrStateClkGateDist::1.1e+09-1.2e+09            0                       # Distribution of time spent in the clock gated state
+system.physmem0.pwrStateClkGateDist::1.2e+09-1.3e+09            0                       # Distribution of time spent in the clock gated state
+system.physmem0.pwrStateClkGateDist::1.3e+09-1.4e+09            0                       # Distribution of time spent in the clock gated state
+system.physmem0.pwrStateClkGateDist::1.4e+09-1.5e+09            0                       # Distribution of time spent in the clock gated state
+system.physmem0.pwrStateClkGateDist::1.5e+09-1.6e+09            0                       # Distribution of time spent in the clock gated state
+system.physmem0.pwrStateClkGateDist::1.6e+09-1.7e+09            0                       # Distribution of time spent in the clock gated state
+system.physmem0.pwrStateClkGateDist::1.7e+09-1.8e+09            0                       # Distribution of time spent in the clock gated state
+system.physmem0.pwrStateClkGateDist::1.8e+09-1.9e+09            0                       # Distribution of time spent in the clock gated state
+system.physmem0.pwrStateClkGateDist::1.9e+09-2e+09            0                       # Distribution of time spent in the clock gated state
+system.physmem0.pwrStateClkGateDist::overflows            0                       # Distribution of time spent in the clock gated state
+system.physmem0.pwrStateClkGateDist::min_value            0                       # Distribution of time spent in the clock gated state
+system.physmem0.pwrStateClkGateDist::max_value            0                       # Distribution of time spent in the clock gated state
+system.physmem0.pwrStateClkGateDist::total            0                       # Distribution of time spent in the clock gated state
+system.physmem0.pwrStateResidencyTicks::UNDEFINED   4467555024                       # Cumulative time (in ticks) in various power states
+system.physmem0.pwrStateResidencyTicks::ON            0                       # Cumulative time (in ticks) in various power states
+system.physmem0.pwrStateResidencyTicks::CLK_GATED            0                       # Cumulative time (in ticks) in various power states
+system.physmem0.pwrStateResidencyTicks::SRAM_RETENTION            0                       # Cumulative time (in ticks) in various power states
+system.physmem0.pwrStateResidencyTicks::OFF            0                       # Cumulative time (in ticks) in various power states
 system.physmem0.bytes_read::cpu.inst        612291324                       # Number of bytes read from this memory
 system.physmem0.bytes_read::cpu.data         97534024                       # Number of bytes read from this memory
 system.physmem0.bytes_read::total           709825348                       # Number of bytes read from this memory
@@ -67,6 +203,40 @@ system.physmem0.bw_write::total               6894251                       # Wr
 system.physmem0.bw_total::cpu.inst          274105779                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem0.bw_total::cpu.data           50557518                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem0.bw_total::total             324663297                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem1.numPwrStateTransitions              0                       # Number of power state transitions
+system.physmem1.pwrStateClkGateDist::samples            0                       # Distribution of time spent in the clock gated state
+system.physmem1.pwrStateClkGateDist::mean          nan                       # Distribution of time spent in the clock gated state
+system.physmem1.pwrStateClkGateDist::stdev          nan                       # Distribution of time spent in the clock gated state
+system.physmem1.pwrStateClkGateDist::underflows            0                       # Distribution of time spent in the clock gated state
+system.physmem1.pwrStateClkGateDist::2-1e+08            0                       # Distribution of time spent in the clock gated state
+system.physmem1.pwrStateClkGateDist::1e+08-2e+08            0                       # Distribution of time spent in the clock gated state
+system.physmem1.pwrStateClkGateDist::2e+08-3e+08            0                       # Distribution of time spent in the clock gated state
+system.physmem1.pwrStateClkGateDist::3e+08-4e+08            0                       # Distribution of time spent in the clock gated state
+system.physmem1.pwrStateClkGateDist::4e+08-5e+08            0                       # Distribution of time spent in the clock gated state
+system.physmem1.pwrStateClkGateDist::5e+08-6e+08            0                       # Distribution of time spent in the clock gated state
+system.physmem1.pwrStateClkGateDist::6e+08-7e+08            0                       # Distribution of time spent in the clock gated state
+system.physmem1.pwrStateClkGateDist::7e+08-8e+08            0                       # Distribution of time spent in the clock gated state
+system.physmem1.pwrStateClkGateDist::8e+08-9e+08            0                       # Distribution of time spent in the clock gated state
+system.physmem1.pwrStateClkGateDist::9e+08-1e+09            0                       # Distribution of time spent in the clock gated state
+system.physmem1.pwrStateClkGateDist::1e+09-1.1e+09            0                       # Distribution of time spent in the clock gated state
+system.physmem1.pwrStateClkGateDist::1.1e+09-1.2e+09            0                       # Distribution of time spent in the clock gated state
+system.physmem1.pwrStateClkGateDist::1.2e+09-1.3e+09            0                       # Distribution of time spent in the clock gated state
+system.physmem1.pwrStateClkGateDist::1.3e+09-1.4e+09            0                       # Distribution of time spent in the clock gated state
+system.physmem1.pwrStateClkGateDist::1.4e+09-1.5e+09            0                       # Distribution of time spent in the clock gated state
+system.physmem1.pwrStateClkGateDist::1.5e+09-1.6e+09            0                       # Distribution of time spent in the clock gated state
+system.physmem1.pwrStateClkGateDist::1.6e+09-1.7e+09            0                       # Distribution of time spent in the clock gated state
+system.physmem1.pwrStateClkGateDist::1.7e+09-1.8e+09            0                       # Distribution of time spent in the clock gated state
+system.physmem1.pwrStateClkGateDist::1.8e+09-1.9e+09            0                       # Distribution of time spent in the clock gated state
+system.physmem1.pwrStateClkGateDist::1.9e+09-2e+09            0                       # Distribution of time spent in the clock gated state
+system.physmem1.pwrStateClkGateDist::overflows            0                       # Distribution of time spent in the clock gated state
+system.physmem1.pwrStateClkGateDist::min_value            0                       # Distribution of time spent in the clock gated state
+system.physmem1.pwrStateClkGateDist::max_value            0                       # Distribution of time spent in the clock gated state
+system.physmem1.pwrStateClkGateDist::total            0                       # Distribution of time spent in the clock gated state
+system.physmem1.pwrStateResidencyTicks::UNDEFINED   4467555024                       # Cumulative time (in ticks) in various power states
+system.physmem1.pwrStateResidencyTicks::ON            0                       # Cumulative time (in ticks) in various power states
+system.physmem1.pwrStateResidencyTicks::CLK_GATED            0                       # Cumulative time (in ticks) in various power states
+system.physmem1.pwrStateResidencyTicks::SRAM_RETENTION            0                       # Cumulative time (in ticks) in various power states
+system.physmem1.pwrStateResidencyTicks::OFF            0                       # Cumulative time (in ticks) in various power states
 system.physmem1.bytes_read::cpu.inst       8318106840                       # Number of bytes read from this memory
 system.physmem1.bytes_read::cpu.data       1495885127                       # Number of bytes read from this memory
 system.physmem1.bytes_read::total          9813991967                       # Number of bytes read from this memory
@@ -91,6 +261,40 @@ system.physmem1.bw_write::total             401682091                       # Wr
 system.physmem1.bw_total::cpu.inst         3723784842                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem1.bw_total::cpu.data         1071348214                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem1.bw_total::total            4795133057                       # Total bandwidth to/from this memory (bytes/s)
+system.rom.numPwrStateTransitions                   0                       # Number of power state transitions
+system.rom.pwrStateClkGateDist::samples             0                       # Distribution of time spent in the clock gated state
+system.rom.pwrStateClkGateDist::mean              nan                       # Distribution of time spent in the clock gated state
+system.rom.pwrStateClkGateDist::stdev             nan                       # Distribution of time spent in the clock gated state
+system.rom.pwrStateClkGateDist::underflows            0                       # Distribution of time spent in the clock gated state
+system.rom.pwrStateClkGateDist::2-1e+08             0                       # Distribution of time spent in the clock gated state
+system.rom.pwrStateClkGateDist::1e+08-2e+08            0                       # Distribution of time spent in the clock gated state
+system.rom.pwrStateClkGateDist::2e+08-3e+08            0                       # Distribution of time spent in the clock gated state
+system.rom.pwrStateClkGateDist::3e+08-4e+08            0                       # Distribution of time spent in the clock gated state
+system.rom.pwrStateClkGateDist::4e+08-5e+08            0                       # Distribution of time spent in the clock gated state
+system.rom.pwrStateClkGateDist::5e+08-6e+08            0                       # Distribution of time spent in the clock gated state
+system.rom.pwrStateClkGateDist::6e+08-7e+08            0                       # Distribution of time spent in the clock gated state
+system.rom.pwrStateClkGateDist::7e+08-8e+08            0                       # Distribution of time spent in the clock gated state
+system.rom.pwrStateClkGateDist::8e+08-9e+08            0                       # Distribution of time spent in the clock gated state
+system.rom.pwrStateClkGateDist::9e+08-1e+09            0                       # Distribution of time spent in the clock gated state
+system.rom.pwrStateClkGateDist::1e+09-1.1e+09            0                       # Distribution of time spent in the clock gated state
+system.rom.pwrStateClkGateDist::1.1e+09-1.2e+09            0                       # Distribution of time spent in the clock gated state
+system.rom.pwrStateClkGateDist::1.2e+09-1.3e+09            0                       # Distribution of time spent in the clock gated state
+system.rom.pwrStateClkGateDist::1.3e+09-1.4e+09            0                       # Distribution of time spent in the clock gated state
+system.rom.pwrStateClkGateDist::1.4e+09-1.5e+09            0                       # Distribution of time spent in the clock gated state
+system.rom.pwrStateClkGateDist::1.5e+09-1.6e+09            0                       # Distribution of time spent in the clock gated state
+system.rom.pwrStateClkGateDist::1.6e+09-1.7e+09            0                       # Distribution of time spent in the clock gated state
+system.rom.pwrStateClkGateDist::1.7e+09-1.8e+09            0                       # Distribution of time spent in the clock gated state
+system.rom.pwrStateClkGateDist::1.8e+09-1.9e+09            0                       # Distribution of time spent in the clock gated state
+system.rom.pwrStateClkGateDist::1.9e+09-2e+09            0                       # Distribution of time spent in the clock gated state
+system.rom.pwrStateClkGateDist::overflows            0                       # Distribution of time spent in the clock gated state
+system.rom.pwrStateClkGateDist::min_value            0                       # Distribution of time spent in the clock gated state
+system.rom.pwrStateClkGateDist::max_value            0                       # Distribution of time spent in the clock gated state
+system.rom.pwrStateClkGateDist::total               0                       # Distribution of time spent in the clock gated state
+system.rom.pwrStateResidencyTicks::UNDEFINED   4467555024                       # Cumulative time (in ticks) in various power states
+system.rom.pwrStateResidencyTicks::ON               0                       # Cumulative time (in ticks) in various power states
+system.rom.pwrStateResidencyTicks::CLK_GATED            0                       # Cumulative time (in ticks) in various power states
+system.rom.pwrStateResidencyTicks::SRAM_RETENTION            0                       # Cumulative time (in ticks) in various power states
+system.rom.pwrStateResidencyTicks::OFF              0                       # Cumulative time (in ticks) in various power states
 system.rom.bytes_read::cpu.inst                432296                       # Number of bytes read from this memory
 system.rom.bytes_read::cpu.data                696392                       # Number of bytes read from this memory
 system.rom.bytes_read::total                  1128688                       # Number of bytes read from this memory
@@ -107,7 +311,109 @@ system.rom.bw_inst_read::total                 193527                       # In
 system.rom.bw_total::cpu.inst                  193527                       # Total bandwidth to/from this memory (bytes/s)
 system.rom.bw_total::cpu.data                  311755                       # Total bandwidth to/from this memory (bytes/s)
 system.rom.bw_total::total                     505282                       # Total bandwidth to/from this memory (bytes/s)
+system.numPwrStateTransitions                       0                       # Number of power state transitions
+system.pwrStateClkGateDist::samples                 0                       # Distribution of time spent in the clock gated state
+system.pwrStateClkGateDist::mean                  nan                       # Distribution of time spent in the clock gated state
+system.pwrStateClkGateDist::stdev                 nan                       # Distribution of time spent in the clock gated state
+system.pwrStateClkGateDist::underflows              0                       # Distribution of time spent in the clock gated state
+system.pwrStateClkGateDist::2-1e+08                 0                       # Distribution of time spent in the clock gated state
+system.pwrStateClkGateDist::1e+08-2e+08             0                       # Distribution of time spent in the clock gated state
+system.pwrStateClkGateDist::2e+08-3e+08             0                       # Distribution of time spent in the clock gated state
+system.pwrStateClkGateDist::3e+08-4e+08             0                       # Distribution of time spent in the clock gated state
+system.pwrStateClkGateDist::4e+08-5e+08             0                       # Distribution of time spent in the clock gated state
+system.pwrStateClkGateDist::5e+08-6e+08             0                       # Distribution of time spent in the clock gated state
+system.pwrStateClkGateDist::6e+08-7e+08             0                       # Distribution of time spent in the clock gated state
+system.pwrStateClkGateDist::7e+08-8e+08             0                       # Distribution of time spent in the clock gated state
+system.pwrStateClkGateDist::8e+08-9e+08             0                       # Distribution of time spent in the clock gated state
+system.pwrStateClkGateDist::9e+08-1e+09             0                       # Distribution of time spent in the clock gated state
+system.pwrStateClkGateDist::1e+09-1.1e+09            0                       # Distribution of time spent in the clock gated state
+system.pwrStateClkGateDist::1.1e+09-1.2e+09            0                       # Distribution of time spent in the clock gated state
+system.pwrStateClkGateDist::1.2e+09-1.3e+09            0                       # Distribution of time spent in the clock gated state
+system.pwrStateClkGateDist::1.3e+09-1.4e+09            0                       # Distribution of time spent in the clock gated state
+system.pwrStateClkGateDist::1.4e+09-1.5e+09            0                       # Distribution of time spent in the clock gated state
+system.pwrStateClkGateDist::1.5e+09-1.6e+09            0                       # Distribution of time spent in the clock gated state
+system.pwrStateClkGateDist::1.6e+09-1.7e+09            0                       # Distribution of time spent in the clock gated state
+system.pwrStateClkGateDist::1.7e+09-1.8e+09            0                       # Distribution of time spent in the clock gated state
+system.pwrStateClkGateDist::1.8e+09-1.9e+09            0                       # Distribution of time spent in the clock gated state
+system.pwrStateClkGateDist::1.9e+09-2e+09            0                       # Distribution of time spent in the clock gated state
+system.pwrStateClkGateDist::overflows               0                       # Distribution of time spent in the clock gated state
+system.pwrStateClkGateDist::min_value               0                       # Distribution of time spent in the clock gated state
+system.pwrStateClkGateDist::max_value               0                       # Distribution of time spent in the clock gated state
+system.pwrStateClkGateDist::total                   0                       # Distribution of time spent in the clock gated state
+system.pwrStateResidencyTicks::UNDEFINED   4467555024                       # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::ON                   0                       # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::CLK_GATED            0                       # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::SRAM_RETENTION            0                       # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::OFF                  0                       # Cumulative time (in ticks) in various power states
+system.bridge.numPwrStateTransitions                0                       # Number of power state transitions
+system.bridge.pwrStateClkGateDist::samples            0                       # Distribution of time spent in the clock gated state
+system.bridge.pwrStateClkGateDist::mean           nan                       # Distribution of time spent in the clock gated state
+system.bridge.pwrStateClkGateDist::stdev          nan                       # Distribution of time spent in the clock gated state
+system.bridge.pwrStateClkGateDist::underflows            0                       # Distribution of time spent in the clock gated state
+system.bridge.pwrStateClkGateDist::2-1e+08            0                       # Distribution of time spent in the clock gated state
+system.bridge.pwrStateClkGateDist::1e+08-2e+08            0                       # Distribution of time spent in the clock gated state
+system.bridge.pwrStateClkGateDist::2e+08-3e+08            0                       # Distribution of time spent in the clock gated state
+system.bridge.pwrStateClkGateDist::3e+08-4e+08            0                       # Distribution of time spent in the clock gated state
+system.bridge.pwrStateClkGateDist::4e+08-5e+08            0                       # Distribution of time spent in the clock gated state
+system.bridge.pwrStateClkGateDist::5e+08-6e+08            0                       # Distribution of time spent in the clock gated state
+system.bridge.pwrStateClkGateDist::6e+08-7e+08            0                       # Distribution of time spent in the clock gated state
+system.bridge.pwrStateClkGateDist::7e+08-8e+08            0                       # Distribution of time spent in the clock gated state
+system.bridge.pwrStateClkGateDist::8e+08-9e+08            0                       # Distribution of time spent in the clock gated state
+system.bridge.pwrStateClkGateDist::9e+08-1e+09            0                       # Distribution of time spent in the clock gated state
+system.bridge.pwrStateClkGateDist::1e+09-1.1e+09            0                       # Distribution of time spent in the clock gated state
+system.bridge.pwrStateClkGateDist::1.1e+09-1.2e+09            0                       # Distribution of time spent in the clock gated state
+system.bridge.pwrStateClkGateDist::1.2e+09-1.3e+09            0                       # Distribution of time spent in the clock gated state
+system.bridge.pwrStateClkGateDist::1.3e+09-1.4e+09            0                       # Distribution of time spent in the clock gated state
+system.bridge.pwrStateClkGateDist::1.4e+09-1.5e+09            0                       # Distribution of time spent in the clock gated state
+system.bridge.pwrStateClkGateDist::1.5e+09-1.6e+09            0                       # Distribution of time spent in the clock gated state
+system.bridge.pwrStateClkGateDist::1.6e+09-1.7e+09            0                       # Distribution of time spent in the clock gated state
+system.bridge.pwrStateClkGateDist::1.7e+09-1.8e+09            0                       # Distribution of time spent in the clock gated state
+system.bridge.pwrStateClkGateDist::1.8e+09-1.9e+09            0                       # Distribution of time spent in the clock gated state
+system.bridge.pwrStateClkGateDist::1.9e+09-2e+09            0                       # Distribution of time spent in the clock gated state
+system.bridge.pwrStateClkGateDist::overflows            0                       # Distribution of time spent in the clock gated state
+system.bridge.pwrStateClkGateDist::min_value            0                       # Distribution of time spent in the clock gated state
+system.bridge.pwrStateClkGateDist::max_value            0                       # Distribution of time spent in the clock gated state
+system.bridge.pwrStateClkGateDist::total            0                       # Distribution of time spent in the clock gated state
+system.bridge.pwrStateResidencyTicks::UNDEFINED   4467555024                       # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::ON            0                       # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::CLK_GATED            0                       # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::SRAM_RETENTION            0                       # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::OFF            0                       # Cumulative time (in ticks) in various power states
 system.cpu_clk_domain.clock                         2                       # Clock period in ticks
+system.cpu.numPwrStateTransitions                   0                       # Number of power state transitions
+system.cpu.pwrStateClkGateDist::samples             0                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::mean              nan                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::stdev             nan                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::underflows            0                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::2-1e+08             0                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1e+08-2e+08            0                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::2e+08-3e+08            0                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::3e+08-4e+08            0                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::4e+08-5e+08            0                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::5e+08-6e+08            0                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::6e+08-7e+08            0                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::7e+08-8e+08            0                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::8e+08-9e+08            0                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::9e+08-1e+09            0                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1e+09-1.1e+09            0                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1.1e+09-1.2e+09            0                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1.2e+09-1.3e+09            0                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1.3e+09-1.4e+09            0                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1.4e+09-1.5e+09            0                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1.5e+09-1.6e+09            0                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1.6e+09-1.7e+09            0                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1.7e+09-1.8e+09            0                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1.8e+09-1.9e+09            0                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1.9e+09-2e+09            0                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::overflows            0                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::min_value            0                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::max_value            0                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::total               0                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateResidencyTicks::UNDEFINED   4467555024                       # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::ON               0                       # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::CLK_GATED            0                       # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::SRAM_RETENTION            0                       # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::OFF              0                       # Cumulative time (in ticks) in various power states
 system.cpu.numCycles                       2233777513                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
@@ -168,6 +474,74 @@ system.cpu.op_class::MemWrite               200199782      8.96%    100.00% # Cl
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                 2233583679                       # Class of executed instruction
+system.disk0.numPwrStateTransitions                 0                       # Number of power state transitions
+system.disk0.pwrStateClkGateDist::samples            0                       # Distribution of time spent in the clock gated state
+system.disk0.pwrStateClkGateDist::mean            nan                       # Distribution of time spent in the clock gated state
+system.disk0.pwrStateClkGateDist::stdev           nan                       # Distribution of time spent in the clock gated state
+system.disk0.pwrStateClkGateDist::underflows            0                       # Distribution of time spent in the clock gated state
+system.disk0.pwrStateClkGateDist::2-1e+08            0                       # Distribution of time spent in the clock gated state
+system.disk0.pwrStateClkGateDist::1e+08-2e+08            0                       # Distribution of time spent in the clock gated state
+system.disk0.pwrStateClkGateDist::2e+08-3e+08            0                       # Distribution of time spent in the clock gated state
+system.disk0.pwrStateClkGateDist::3e+08-4e+08            0                       # Distribution of time spent in the clock gated state
+system.disk0.pwrStateClkGateDist::4e+08-5e+08            0                       # Distribution of time spent in the clock gated state
+system.disk0.pwrStateClkGateDist::5e+08-6e+08            0                       # Distribution of time spent in the clock gated state
+system.disk0.pwrStateClkGateDist::6e+08-7e+08            0                       # Distribution of time spent in the clock gated state
+system.disk0.pwrStateClkGateDist::7e+08-8e+08            0                       # Distribution of time spent in the clock gated state
+system.disk0.pwrStateClkGateDist::8e+08-9e+08            0                       # Distribution of time spent in the clock gated state
+system.disk0.pwrStateClkGateDist::9e+08-1e+09            0                       # Distribution of time spent in the clock gated state
+system.disk0.pwrStateClkGateDist::1e+09-1.1e+09            0                       # Distribution of time spent in the clock gated state
+system.disk0.pwrStateClkGateDist::1.1e+09-1.2e+09            0                       # Distribution of time spent in the clock gated state
+system.disk0.pwrStateClkGateDist::1.2e+09-1.3e+09            0                       # Distribution of time spent in the clock gated state
+system.disk0.pwrStateClkGateDist::1.3e+09-1.4e+09            0                       # Distribution of time spent in the clock gated state
+system.disk0.pwrStateClkGateDist::1.4e+09-1.5e+09            0                       # Distribution of time spent in the clock gated state
+system.disk0.pwrStateClkGateDist::1.5e+09-1.6e+09            0                       # Distribution of time spent in the clock gated state
+system.disk0.pwrStateClkGateDist::1.6e+09-1.7e+09            0                       # Distribution of time spent in the clock gated state
+system.disk0.pwrStateClkGateDist::1.7e+09-1.8e+09            0                       # Distribution of time spent in the clock gated state
+system.disk0.pwrStateClkGateDist::1.8e+09-1.9e+09            0                       # Distribution of time spent in the clock gated state
+system.disk0.pwrStateClkGateDist::1.9e+09-2e+09            0                       # Distribution of time spent in the clock gated state
+system.disk0.pwrStateClkGateDist::overflows            0                       # Distribution of time spent in the clock gated state
+system.disk0.pwrStateClkGateDist::min_value            0                       # Distribution of time spent in the clock gated state
+system.disk0.pwrStateClkGateDist::max_value            0                       # Distribution of time spent in the clock gated state
+system.disk0.pwrStateClkGateDist::total             0                       # Distribution of time spent in the clock gated state
+system.disk0.pwrStateResidencyTicks::UNDEFINED   4467555024                       # Cumulative time (in ticks) in various power states
+system.disk0.pwrStateResidencyTicks::ON             0                       # Cumulative time (in ticks) in various power states
+system.disk0.pwrStateResidencyTicks::CLK_GATED            0                       # Cumulative time (in ticks) in various power states
+system.disk0.pwrStateResidencyTicks::SRAM_RETENTION            0                       # Cumulative time (in ticks) in various power states
+system.disk0.pwrStateResidencyTicks::OFF            0                       # Cumulative time (in ticks) in various power states
+system.iobus.numPwrStateTransitions                 0                       # Number of power state transitions
+system.iobus.pwrStateClkGateDist::samples            0                       # Distribution of time spent in the clock gated state
+system.iobus.pwrStateClkGateDist::mean            nan                       # Distribution of time spent in the clock gated state
+system.iobus.pwrStateClkGateDist::stdev           nan                       # Distribution of time spent in the clock gated state
+system.iobus.pwrStateClkGateDist::underflows            0                       # Distribution of time spent in the clock gated state
+system.iobus.pwrStateClkGateDist::2-1e+08            0                       # Distribution of time spent in the clock gated state
+system.iobus.pwrStateClkGateDist::1e+08-2e+08            0                       # Distribution of time spent in the clock gated state
+system.iobus.pwrStateClkGateDist::2e+08-3e+08            0                       # Distribution of time spent in the clock gated state
+system.iobus.pwrStateClkGateDist::3e+08-4e+08            0                       # Distribution of time spent in the clock gated state
+system.iobus.pwrStateClkGateDist::4e+08-5e+08            0                       # Distribution of time spent in the clock gated state
+system.iobus.pwrStateClkGateDist::5e+08-6e+08            0                       # Distribution of time spent in the clock gated state
+system.iobus.pwrStateClkGateDist::6e+08-7e+08            0                       # Distribution of time spent in the clock gated state
+system.iobus.pwrStateClkGateDist::7e+08-8e+08            0                       # Distribution of time spent in the clock gated state
+system.iobus.pwrStateClkGateDist::8e+08-9e+08            0                       # Distribution of time spent in the clock gated state
+system.iobus.pwrStateClkGateDist::9e+08-1e+09            0                       # Distribution of time spent in the clock gated state
+system.iobus.pwrStateClkGateDist::1e+09-1.1e+09            0                       # Distribution of time spent in the clock gated state
+system.iobus.pwrStateClkGateDist::1.1e+09-1.2e+09            0                       # Distribution of time spent in the clock gated state
+system.iobus.pwrStateClkGateDist::1.2e+09-1.3e+09            0                       # Distribution of time spent in the clock gated state
+system.iobus.pwrStateClkGateDist::1.3e+09-1.4e+09            0                       # Distribution of time spent in the clock gated state
+system.iobus.pwrStateClkGateDist::1.4e+09-1.5e+09            0                       # Distribution of time spent in the clock gated state
+system.iobus.pwrStateClkGateDist::1.5e+09-1.6e+09            0                       # Distribution of time spent in the clock gated state
+system.iobus.pwrStateClkGateDist::1.6e+09-1.7e+09            0                       # Distribution of time spent in the clock gated state
+system.iobus.pwrStateClkGateDist::1.7e+09-1.8e+09            0                       # Distribution of time spent in the clock gated state
+system.iobus.pwrStateClkGateDist::1.8e+09-1.9e+09            0                       # Distribution of time spent in the clock gated state
+system.iobus.pwrStateClkGateDist::1.9e+09-2e+09            0                       # Distribution of time spent in the clock gated state
+system.iobus.pwrStateClkGateDist::overflows            0                       # Distribution of time spent in the clock gated state
+system.iobus.pwrStateClkGateDist::min_value            0                       # Distribution of time spent in the clock gated state
+system.iobus.pwrStateClkGateDist::max_value            0                       # Distribution of time spent in the clock gated state
+system.iobus.pwrStateClkGateDist::total             0                       # Distribution of time spent in the clock gated state
+system.iobus.pwrStateResidencyTicks::UNDEFINED   4467555024                       # Cumulative time (in ticks) in various power states
+system.iobus.pwrStateResidencyTicks::ON             0                       # Cumulative time (in ticks) in various power states
+system.iobus.pwrStateResidencyTicks::CLK_GATED            0                       # Cumulative time (in ticks) in various power states
+system.iobus.pwrStateResidencyTicks::SRAM_RETENTION            0                       # Cumulative time (in ticks) in various power states
+system.iobus.pwrStateResidencyTicks::OFF            0                       # Cumulative time (in ticks) in various power states
 system.iobus.trans_dist::ReadReq              4348554                       # Transaction distribution
 system.iobus.trans_dist::ReadResp             4348554                       # Transaction distribution
 system.iobus.trans_dist::WriteReq                7569                       # Transaction distribution
@@ -200,6 +574,40 @@ system.iobus.pkt_size_system.bridge.master::system.t1000.puart0.pio        14609
 system.iobus.pkt_size_system.bridge.master::system.t1000.hvuart.pio           18                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.disk0.pio     34731524                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total     34746591                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.numPwrStateTransitions                0                       # Number of power state transitions
+system.membus.pwrStateClkGateDist::samples            0                       # Distribution of time spent in the clock gated state
+system.membus.pwrStateClkGateDist::mean           nan                       # Distribution of time spent in the clock gated state
+system.membus.pwrStateClkGateDist::stdev          nan                       # Distribution of time spent in the clock gated state
+system.membus.pwrStateClkGateDist::underflows            0                       # Distribution of time spent in the clock gated state
+system.membus.pwrStateClkGateDist::2-1e+08            0                       # Distribution of time spent in the clock gated state
+system.membus.pwrStateClkGateDist::1e+08-2e+08            0                       # Distribution of time spent in the clock gated state
+system.membus.pwrStateClkGateDist::2e+08-3e+08            0                       # Distribution of time spent in the clock gated state
+system.membus.pwrStateClkGateDist::3e+08-4e+08            0                       # Distribution of time spent in the clock gated state
+system.membus.pwrStateClkGateDist::4e+08-5e+08            0                       # Distribution of time spent in the clock gated state
+system.membus.pwrStateClkGateDist::5e+08-6e+08            0                       # Distribution of time spent in the clock gated state
+system.membus.pwrStateClkGateDist::6e+08-7e+08            0                       # Distribution of time spent in the clock gated state
+system.membus.pwrStateClkGateDist::7e+08-8e+08            0                       # Distribution of time spent in the clock gated state
+system.membus.pwrStateClkGateDist::8e+08-9e+08            0                       # Distribution of time spent in the clock gated state
+system.membus.pwrStateClkGateDist::9e+08-1e+09            0                       # Distribution of time spent in the clock gated state
+system.membus.pwrStateClkGateDist::1e+09-1.1e+09            0                       # Distribution of time spent in the clock gated state
+system.membus.pwrStateClkGateDist::1.1e+09-1.2e+09            0                       # Distribution of time spent in the clock gated state
+system.membus.pwrStateClkGateDist::1.2e+09-1.3e+09            0                       # Distribution of time spent in the clock gated state
+system.membus.pwrStateClkGateDist::1.3e+09-1.4e+09            0                       # Distribution of time spent in the clock gated state
+system.membus.pwrStateClkGateDist::1.4e+09-1.5e+09            0                       # Distribution of time spent in the clock gated state
+system.membus.pwrStateClkGateDist::1.5e+09-1.6e+09            0                       # Distribution of time spent in the clock gated state
+system.membus.pwrStateClkGateDist::1.6e+09-1.7e+09            0                       # Distribution of time spent in the clock gated state
+system.membus.pwrStateClkGateDist::1.7e+09-1.8e+09            0                       # Distribution of time spent in the clock gated state
+system.membus.pwrStateClkGateDist::1.8e+09-1.9e+09            0                       # Distribution of time spent in the clock gated state
+system.membus.pwrStateClkGateDist::1.9e+09-2e+09            0                       # Distribution of time spent in the clock gated state
+system.membus.pwrStateClkGateDist::overflows            0                       # Distribution of time spent in the clock gated state
+system.membus.pwrStateClkGateDist::min_value            0                       # Distribution of time spent in the clock gated state
+system.membus.pwrStateClkGateDist::max_value            0                       # Distribution of time spent in the clock gated state
+system.membus.pwrStateClkGateDist::total            0                       # Distribution of time spent in the clock gated state
+system.membus.pwrStateResidencyTicks::UNDEFINED   4467555024                       # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::ON            0                       # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::CLK_GATED            0                       # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::SRAM_RETENTION            0                       # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::OFF            0                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadReq          2573267624                       # Transaction distribution
 system.membus.trans_dist::ReadResp         2573267624                       # Transaction distribution
 system.membus.trans_dist::WriteReq          189322556                       # Transaction distribution
@@ -247,5 +655,583 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::total          2767993261                       # Request fanout histogram
+system.membus.badaddr_responder.numPwrStateTransitions            0                       # Number of power state transitions
+system.membus.badaddr_responder.pwrStateClkGateDist::samples            0                       # Distribution of time spent in the clock gated state
+system.membus.badaddr_responder.pwrStateClkGateDist::mean          nan                       # Distribution of time spent in the clock gated state
+system.membus.badaddr_responder.pwrStateClkGateDist::stdev          nan                       # Distribution of time spent in the clock gated state
+system.membus.badaddr_responder.pwrStateClkGateDist::underflows            0                       # Distribution of time spent in the clock gated state
+system.membus.badaddr_responder.pwrStateClkGateDist::2-1e+08            0                       # Distribution of time spent in the clock gated state
+system.membus.badaddr_responder.pwrStateClkGateDist::1e+08-2e+08            0                       # Distribution of time spent in the clock gated state
+system.membus.badaddr_responder.pwrStateClkGateDist::2e+08-3e+08            0                       # Distribution of time spent in the clock gated state
+system.membus.badaddr_responder.pwrStateClkGateDist::3e+08-4e+08            0                       # Distribution of time spent in the clock gated state
+system.membus.badaddr_responder.pwrStateClkGateDist::4e+08-5e+08            0                       # Distribution of time spent in the clock gated state
+system.membus.badaddr_responder.pwrStateClkGateDist::5e+08-6e+08            0                       # Distribution of time spent in the clock gated state
+system.membus.badaddr_responder.pwrStateClkGateDist::6e+08-7e+08            0                       # Distribution of time spent in the clock gated state
+system.membus.badaddr_responder.pwrStateClkGateDist::7e+08-8e+08            0                       # Distribution of time spent in the clock gated state
+system.membus.badaddr_responder.pwrStateClkGateDist::8e+08-9e+08            0                       # Distribution of time spent in the clock gated state
+system.membus.badaddr_responder.pwrStateClkGateDist::9e+08-1e+09            0                       # Distribution of time spent in the clock gated state
+system.membus.badaddr_responder.pwrStateClkGateDist::1e+09-1.1e+09            0                       # Distribution of time spent in the clock gated state
+system.membus.badaddr_responder.pwrStateClkGateDist::1.1e+09-1.2e+09            0                       # Distribution of time spent in the clock gated state
+system.membus.badaddr_responder.pwrStateClkGateDist::1.2e+09-1.3e+09            0                       # Distribution of time spent in the clock gated state
+system.membus.badaddr_responder.pwrStateClkGateDist::1.3e+09-1.4e+09            0                       # Distribution of time spent in the clock gated state
+system.membus.badaddr_responder.pwrStateClkGateDist::1.4e+09-1.5e+09            0                       # Distribution of time spent in the clock gated state
+system.membus.badaddr_responder.pwrStateClkGateDist::1.5e+09-1.6e+09            0                       # Distribution of time spent in the clock gated state
+system.membus.badaddr_responder.pwrStateClkGateDist::1.6e+09-1.7e+09            0                       # Distribution of time spent in the clock gated state
+system.membus.badaddr_responder.pwrStateClkGateDist::1.7e+09-1.8e+09            0                       # Distribution of time spent in the clock gated state
+system.membus.badaddr_responder.pwrStateClkGateDist::1.8e+09-1.9e+09            0                       # Distribution of time spent in the clock gated state
+system.membus.badaddr_responder.pwrStateClkGateDist::1.9e+09-2e+09            0                       # Distribution of time spent in the clock gated state
+system.membus.badaddr_responder.pwrStateClkGateDist::overflows            0                       # Distribution of time spent in the clock gated state
+system.membus.badaddr_responder.pwrStateClkGateDist::min_value            0                       # Distribution of time spent in the clock gated state
+system.membus.badaddr_responder.pwrStateClkGateDist::max_value            0                       # Distribution of time spent in the clock gated state
+system.membus.badaddr_responder.pwrStateClkGateDist::total            0                       # Distribution of time spent in the clock gated state
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED   4467555024                       # Cumulative time (in ticks) in various power states
+system.membus.badaddr_responder.pwrStateResidencyTicks::ON            0                       # Cumulative time (in ticks) in various power states
+system.membus.badaddr_responder.pwrStateResidencyTicks::CLK_GATED            0                       # Cumulative time (in ticks) in various power states
+system.membus.badaddr_responder.pwrStateResidencyTicks::SRAM_RETENTION            0                       # Cumulative time (in ticks) in various power states
+system.membus.badaddr_responder.pwrStateResidencyTicks::OFF            0                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_clk.numPwrStateTransitions            0                       # Number of power state transitions
+system.t1000.fake_clk.pwrStateClkGateDist::samples            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_clk.pwrStateClkGateDist::mean          nan                       # Distribution of time spent in the clock gated state
+system.t1000.fake_clk.pwrStateClkGateDist::stdev          nan                       # Distribution of time spent in the clock gated state
+system.t1000.fake_clk.pwrStateClkGateDist::underflows            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_clk.pwrStateClkGateDist::2-1e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_clk.pwrStateClkGateDist::1e+08-2e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_clk.pwrStateClkGateDist::2e+08-3e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_clk.pwrStateClkGateDist::3e+08-4e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_clk.pwrStateClkGateDist::4e+08-5e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_clk.pwrStateClkGateDist::5e+08-6e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_clk.pwrStateClkGateDist::6e+08-7e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_clk.pwrStateClkGateDist::7e+08-8e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_clk.pwrStateClkGateDist::8e+08-9e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_clk.pwrStateClkGateDist::9e+08-1e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_clk.pwrStateClkGateDist::1e+09-1.1e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_clk.pwrStateClkGateDist::1.1e+09-1.2e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_clk.pwrStateClkGateDist::1.2e+09-1.3e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_clk.pwrStateClkGateDist::1.3e+09-1.4e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_clk.pwrStateClkGateDist::1.4e+09-1.5e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_clk.pwrStateClkGateDist::1.5e+09-1.6e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_clk.pwrStateClkGateDist::1.6e+09-1.7e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_clk.pwrStateClkGateDist::1.7e+09-1.8e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_clk.pwrStateClkGateDist::1.8e+09-1.9e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_clk.pwrStateClkGateDist::1.9e+09-2e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_clk.pwrStateClkGateDist::overflows            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_clk.pwrStateClkGateDist::min_value            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_clk.pwrStateClkGateDist::max_value            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_clk.pwrStateClkGateDist::total            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_clk.pwrStateResidencyTicks::UNDEFINED   4467555024                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_clk.pwrStateResidencyTicks::ON            0                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_clk.pwrStateResidencyTicks::CLK_GATED            0                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_clk.pwrStateResidencyTicks::SRAM_RETENTION            0                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_clk.pwrStateResidencyTicks::OFF            0                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_jbi.numPwrStateTransitions            0                       # Number of power state transitions
+system.t1000.fake_jbi.pwrStateClkGateDist::samples            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_jbi.pwrStateClkGateDist::mean          nan                       # Distribution of time spent in the clock gated state
+system.t1000.fake_jbi.pwrStateClkGateDist::stdev          nan                       # Distribution of time spent in the clock gated state
+system.t1000.fake_jbi.pwrStateClkGateDist::underflows            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_jbi.pwrStateClkGateDist::2-1e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_jbi.pwrStateClkGateDist::1e+08-2e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_jbi.pwrStateClkGateDist::2e+08-3e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_jbi.pwrStateClkGateDist::3e+08-4e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_jbi.pwrStateClkGateDist::4e+08-5e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_jbi.pwrStateClkGateDist::5e+08-6e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_jbi.pwrStateClkGateDist::6e+08-7e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_jbi.pwrStateClkGateDist::7e+08-8e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_jbi.pwrStateClkGateDist::8e+08-9e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_jbi.pwrStateClkGateDist::9e+08-1e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_jbi.pwrStateClkGateDist::1e+09-1.1e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_jbi.pwrStateClkGateDist::1.1e+09-1.2e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_jbi.pwrStateClkGateDist::1.2e+09-1.3e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_jbi.pwrStateClkGateDist::1.3e+09-1.4e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_jbi.pwrStateClkGateDist::1.4e+09-1.5e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_jbi.pwrStateClkGateDist::1.5e+09-1.6e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_jbi.pwrStateClkGateDist::1.6e+09-1.7e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_jbi.pwrStateClkGateDist::1.7e+09-1.8e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_jbi.pwrStateClkGateDist::1.8e+09-1.9e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_jbi.pwrStateClkGateDist::1.9e+09-2e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_jbi.pwrStateClkGateDist::overflows            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_jbi.pwrStateClkGateDist::min_value            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_jbi.pwrStateClkGateDist::max_value            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_jbi.pwrStateClkGateDist::total            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_jbi.pwrStateResidencyTicks::UNDEFINED   4467555024                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_jbi.pwrStateResidencyTicks::ON            0                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_jbi.pwrStateResidencyTicks::CLK_GATED            0                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_jbi.pwrStateResidencyTicks::SRAM_RETENTION            0                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_jbi.pwrStateResidencyTicks::OFF            0                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_l2_1.numPwrStateTransitions            0                       # Number of power state transitions
+system.t1000.fake_l2_1.pwrStateClkGateDist::samples            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_1.pwrStateClkGateDist::mean          nan                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_1.pwrStateClkGateDist::stdev          nan                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_1.pwrStateClkGateDist::underflows            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_1.pwrStateClkGateDist::2-1e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_1.pwrStateClkGateDist::1e+08-2e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_1.pwrStateClkGateDist::2e+08-3e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_1.pwrStateClkGateDist::3e+08-4e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_1.pwrStateClkGateDist::4e+08-5e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_1.pwrStateClkGateDist::5e+08-6e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_1.pwrStateClkGateDist::6e+08-7e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_1.pwrStateClkGateDist::7e+08-8e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_1.pwrStateClkGateDist::8e+08-9e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_1.pwrStateClkGateDist::9e+08-1e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_1.pwrStateClkGateDist::1e+09-1.1e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_1.pwrStateClkGateDist::1.1e+09-1.2e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_1.pwrStateClkGateDist::1.2e+09-1.3e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_1.pwrStateClkGateDist::1.3e+09-1.4e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_1.pwrStateClkGateDist::1.4e+09-1.5e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_1.pwrStateClkGateDist::1.5e+09-1.6e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_1.pwrStateClkGateDist::1.6e+09-1.7e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_1.pwrStateClkGateDist::1.7e+09-1.8e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_1.pwrStateClkGateDist::1.8e+09-1.9e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_1.pwrStateClkGateDist::1.9e+09-2e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_1.pwrStateClkGateDist::overflows            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_1.pwrStateClkGateDist::min_value            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_1.pwrStateClkGateDist::max_value            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_1.pwrStateClkGateDist::total            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_1.pwrStateResidencyTicks::UNDEFINED   4467555024                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_l2_1.pwrStateResidencyTicks::ON            0                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_l2_1.pwrStateResidencyTicks::CLK_GATED            0                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_l2_1.pwrStateResidencyTicks::SRAM_RETENTION            0                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_l2_1.pwrStateResidencyTicks::OFF            0                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_l2_2.numPwrStateTransitions            0                       # Number of power state transitions
+system.t1000.fake_l2_2.pwrStateClkGateDist::samples            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_2.pwrStateClkGateDist::mean          nan                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_2.pwrStateClkGateDist::stdev          nan                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_2.pwrStateClkGateDist::underflows            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_2.pwrStateClkGateDist::2-1e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_2.pwrStateClkGateDist::1e+08-2e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_2.pwrStateClkGateDist::2e+08-3e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_2.pwrStateClkGateDist::3e+08-4e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_2.pwrStateClkGateDist::4e+08-5e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_2.pwrStateClkGateDist::5e+08-6e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_2.pwrStateClkGateDist::6e+08-7e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_2.pwrStateClkGateDist::7e+08-8e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_2.pwrStateClkGateDist::8e+08-9e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_2.pwrStateClkGateDist::9e+08-1e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_2.pwrStateClkGateDist::1e+09-1.1e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_2.pwrStateClkGateDist::1.1e+09-1.2e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_2.pwrStateClkGateDist::1.2e+09-1.3e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_2.pwrStateClkGateDist::1.3e+09-1.4e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_2.pwrStateClkGateDist::1.4e+09-1.5e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_2.pwrStateClkGateDist::1.5e+09-1.6e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_2.pwrStateClkGateDist::1.6e+09-1.7e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_2.pwrStateClkGateDist::1.7e+09-1.8e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_2.pwrStateClkGateDist::1.8e+09-1.9e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_2.pwrStateClkGateDist::1.9e+09-2e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_2.pwrStateClkGateDist::overflows            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_2.pwrStateClkGateDist::min_value            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_2.pwrStateClkGateDist::max_value            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_2.pwrStateClkGateDist::total            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_2.pwrStateResidencyTicks::UNDEFINED   4467555024                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_l2_2.pwrStateResidencyTicks::ON            0                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_l2_2.pwrStateResidencyTicks::CLK_GATED            0                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_l2_2.pwrStateResidencyTicks::SRAM_RETENTION            0                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_l2_2.pwrStateResidencyTicks::OFF            0                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_l2_3.numPwrStateTransitions            0                       # Number of power state transitions
+system.t1000.fake_l2_3.pwrStateClkGateDist::samples            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_3.pwrStateClkGateDist::mean          nan                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_3.pwrStateClkGateDist::stdev          nan                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_3.pwrStateClkGateDist::underflows            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_3.pwrStateClkGateDist::2-1e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_3.pwrStateClkGateDist::1e+08-2e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_3.pwrStateClkGateDist::2e+08-3e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_3.pwrStateClkGateDist::3e+08-4e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_3.pwrStateClkGateDist::4e+08-5e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_3.pwrStateClkGateDist::5e+08-6e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_3.pwrStateClkGateDist::6e+08-7e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_3.pwrStateClkGateDist::7e+08-8e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_3.pwrStateClkGateDist::8e+08-9e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_3.pwrStateClkGateDist::9e+08-1e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_3.pwrStateClkGateDist::1e+09-1.1e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_3.pwrStateClkGateDist::1.1e+09-1.2e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_3.pwrStateClkGateDist::1.2e+09-1.3e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_3.pwrStateClkGateDist::1.3e+09-1.4e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_3.pwrStateClkGateDist::1.4e+09-1.5e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_3.pwrStateClkGateDist::1.5e+09-1.6e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_3.pwrStateClkGateDist::1.6e+09-1.7e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_3.pwrStateClkGateDist::1.7e+09-1.8e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_3.pwrStateClkGateDist::1.8e+09-1.9e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_3.pwrStateClkGateDist::1.9e+09-2e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_3.pwrStateClkGateDist::overflows            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_3.pwrStateClkGateDist::min_value            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_3.pwrStateClkGateDist::max_value            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_3.pwrStateClkGateDist::total            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_3.pwrStateResidencyTicks::UNDEFINED   4467555024                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_l2_3.pwrStateResidencyTicks::ON            0                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_l2_3.pwrStateResidencyTicks::CLK_GATED            0                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_l2_3.pwrStateResidencyTicks::SRAM_RETENTION            0                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_l2_3.pwrStateResidencyTicks::OFF            0                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_l2_4.numPwrStateTransitions            0                       # Number of power state transitions
+system.t1000.fake_l2_4.pwrStateClkGateDist::samples            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_4.pwrStateClkGateDist::mean          nan                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_4.pwrStateClkGateDist::stdev          nan                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_4.pwrStateClkGateDist::underflows            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_4.pwrStateClkGateDist::2-1e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_4.pwrStateClkGateDist::1e+08-2e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_4.pwrStateClkGateDist::2e+08-3e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_4.pwrStateClkGateDist::3e+08-4e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_4.pwrStateClkGateDist::4e+08-5e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_4.pwrStateClkGateDist::5e+08-6e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_4.pwrStateClkGateDist::6e+08-7e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_4.pwrStateClkGateDist::7e+08-8e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_4.pwrStateClkGateDist::8e+08-9e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_4.pwrStateClkGateDist::9e+08-1e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_4.pwrStateClkGateDist::1e+09-1.1e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_4.pwrStateClkGateDist::1.1e+09-1.2e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_4.pwrStateClkGateDist::1.2e+09-1.3e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_4.pwrStateClkGateDist::1.3e+09-1.4e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_4.pwrStateClkGateDist::1.4e+09-1.5e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_4.pwrStateClkGateDist::1.5e+09-1.6e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_4.pwrStateClkGateDist::1.6e+09-1.7e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_4.pwrStateClkGateDist::1.7e+09-1.8e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_4.pwrStateClkGateDist::1.8e+09-1.9e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_4.pwrStateClkGateDist::1.9e+09-2e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_4.pwrStateClkGateDist::overflows            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_4.pwrStateClkGateDist::min_value            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_4.pwrStateClkGateDist::max_value            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_4.pwrStateClkGateDist::total            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2_4.pwrStateResidencyTicks::UNDEFINED   4467555024                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_l2_4.pwrStateResidencyTicks::ON            0                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_l2_4.pwrStateResidencyTicks::CLK_GATED            0                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_l2_4.pwrStateResidencyTicks::SRAM_RETENTION            0                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_l2_4.pwrStateResidencyTicks::OFF            0                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_l2esr_1.numPwrStateTransitions            0                       # Number of power state transitions
+system.t1000.fake_l2esr_1.pwrStateClkGateDist::samples            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_1.pwrStateClkGateDist::mean          nan                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_1.pwrStateClkGateDist::stdev          nan                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_1.pwrStateClkGateDist::underflows            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_1.pwrStateClkGateDist::2-1e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_1.pwrStateClkGateDist::1e+08-2e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_1.pwrStateClkGateDist::2e+08-3e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_1.pwrStateClkGateDist::3e+08-4e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_1.pwrStateClkGateDist::4e+08-5e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_1.pwrStateClkGateDist::5e+08-6e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_1.pwrStateClkGateDist::6e+08-7e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_1.pwrStateClkGateDist::7e+08-8e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_1.pwrStateClkGateDist::8e+08-9e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_1.pwrStateClkGateDist::9e+08-1e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_1.pwrStateClkGateDist::1e+09-1.1e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_1.pwrStateClkGateDist::1.1e+09-1.2e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_1.pwrStateClkGateDist::1.2e+09-1.3e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_1.pwrStateClkGateDist::1.3e+09-1.4e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_1.pwrStateClkGateDist::1.4e+09-1.5e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_1.pwrStateClkGateDist::1.5e+09-1.6e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_1.pwrStateClkGateDist::1.6e+09-1.7e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_1.pwrStateClkGateDist::1.7e+09-1.8e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_1.pwrStateClkGateDist::1.8e+09-1.9e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_1.pwrStateClkGateDist::1.9e+09-2e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_1.pwrStateClkGateDist::overflows            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_1.pwrStateClkGateDist::min_value            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_1.pwrStateClkGateDist::max_value            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_1.pwrStateClkGateDist::total            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_1.pwrStateResidencyTicks::UNDEFINED   4467555024                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_l2esr_1.pwrStateResidencyTicks::ON            0                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_l2esr_1.pwrStateResidencyTicks::CLK_GATED            0                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_l2esr_1.pwrStateResidencyTicks::SRAM_RETENTION            0                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_l2esr_1.pwrStateResidencyTicks::OFF            0                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_l2esr_2.numPwrStateTransitions            0                       # Number of power state transitions
+system.t1000.fake_l2esr_2.pwrStateClkGateDist::samples            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_2.pwrStateClkGateDist::mean          nan                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_2.pwrStateClkGateDist::stdev          nan                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_2.pwrStateClkGateDist::underflows            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_2.pwrStateClkGateDist::2-1e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_2.pwrStateClkGateDist::1e+08-2e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_2.pwrStateClkGateDist::2e+08-3e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_2.pwrStateClkGateDist::3e+08-4e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_2.pwrStateClkGateDist::4e+08-5e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_2.pwrStateClkGateDist::5e+08-6e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_2.pwrStateClkGateDist::6e+08-7e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_2.pwrStateClkGateDist::7e+08-8e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_2.pwrStateClkGateDist::8e+08-9e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_2.pwrStateClkGateDist::9e+08-1e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_2.pwrStateClkGateDist::1e+09-1.1e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_2.pwrStateClkGateDist::1.1e+09-1.2e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_2.pwrStateClkGateDist::1.2e+09-1.3e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_2.pwrStateClkGateDist::1.3e+09-1.4e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_2.pwrStateClkGateDist::1.4e+09-1.5e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_2.pwrStateClkGateDist::1.5e+09-1.6e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_2.pwrStateClkGateDist::1.6e+09-1.7e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_2.pwrStateClkGateDist::1.7e+09-1.8e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_2.pwrStateClkGateDist::1.8e+09-1.9e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_2.pwrStateClkGateDist::1.9e+09-2e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_2.pwrStateClkGateDist::overflows            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_2.pwrStateClkGateDist::min_value            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_2.pwrStateClkGateDist::max_value            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_2.pwrStateClkGateDist::total            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_2.pwrStateResidencyTicks::UNDEFINED   4467555024                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_l2esr_2.pwrStateResidencyTicks::ON            0                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_l2esr_2.pwrStateResidencyTicks::CLK_GATED            0                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_l2esr_2.pwrStateResidencyTicks::SRAM_RETENTION            0                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_l2esr_2.pwrStateResidencyTicks::OFF            0                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_l2esr_3.numPwrStateTransitions            0                       # Number of power state transitions
+system.t1000.fake_l2esr_3.pwrStateClkGateDist::samples            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_3.pwrStateClkGateDist::mean          nan                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_3.pwrStateClkGateDist::stdev          nan                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_3.pwrStateClkGateDist::underflows            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_3.pwrStateClkGateDist::2-1e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_3.pwrStateClkGateDist::1e+08-2e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_3.pwrStateClkGateDist::2e+08-3e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_3.pwrStateClkGateDist::3e+08-4e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_3.pwrStateClkGateDist::4e+08-5e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_3.pwrStateClkGateDist::5e+08-6e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_3.pwrStateClkGateDist::6e+08-7e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_3.pwrStateClkGateDist::7e+08-8e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_3.pwrStateClkGateDist::8e+08-9e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_3.pwrStateClkGateDist::9e+08-1e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_3.pwrStateClkGateDist::1e+09-1.1e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_3.pwrStateClkGateDist::1.1e+09-1.2e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_3.pwrStateClkGateDist::1.2e+09-1.3e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_3.pwrStateClkGateDist::1.3e+09-1.4e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_3.pwrStateClkGateDist::1.4e+09-1.5e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_3.pwrStateClkGateDist::1.5e+09-1.6e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_3.pwrStateClkGateDist::1.6e+09-1.7e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_3.pwrStateClkGateDist::1.7e+09-1.8e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_3.pwrStateClkGateDist::1.8e+09-1.9e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_3.pwrStateClkGateDist::1.9e+09-2e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_3.pwrStateClkGateDist::overflows            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_3.pwrStateClkGateDist::min_value            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_3.pwrStateClkGateDist::max_value            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_3.pwrStateClkGateDist::total            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_3.pwrStateResidencyTicks::UNDEFINED   4467555024                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_l2esr_3.pwrStateResidencyTicks::ON            0                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_l2esr_3.pwrStateResidencyTicks::CLK_GATED            0                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_l2esr_3.pwrStateResidencyTicks::SRAM_RETENTION            0                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_l2esr_3.pwrStateResidencyTicks::OFF            0                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_l2esr_4.numPwrStateTransitions            0                       # Number of power state transitions
+system.t1000.fake_l2esr_4.pwrStateClkGateDist::samples            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_4.pwrStateClkGateDist::mean          nan                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_4.pwrStateClkGateDist::stdev          nan                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_4.pwrStateClkGateDist::underflows            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_4.pwrStateClkGateDist::2-1e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_4.pwrStateClkGateDist::1e+08-2e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_4.pwrStateClkGateDist::2e+08-3e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_4.pwrStateClkGateDist::3e+08-4e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_4.pwrStateClkGateDist::4e+08-5e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_4.pwrStateClkGateDist::5e+08-6e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_4.pwrStateClkGateDist::6e+08-7e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_4.pwrStateClkGateDist::7e+08-8e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_4.pwrStateClkGateDist::8e+08-9e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_4.pwrStateClkGateDist::9e+08-1e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_4.pwrStateClkGateDist::1e+09-1.1e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_4.pwrStateClkGateDist::1.1e+09-1.2e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_4.pwrStateClkGateDist::1.2e+09-1.3e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_4.pwrStateClkGateDist::1.3e+09-1.4e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_4.pwrStateClkGateDist::1.4e+09-1.5e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_4.pwrStateClkGateDist::1.5e+09-1.6e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_4.pwrStateClkGateDist::1.6e+09-1.7e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_4.pwrStateClkGateDist::1.7e+09-1.8e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_4.pwrStateClkGateDist::1.8e+09-1.9e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_4.pwrStateClkGateDist::1.9e+09-2e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_4.pwrStateClkGateDist::overflows            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_4.pwrStateClkGateDist::min_value            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_4.pwrStateClkGateDist::max_value            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_4.pwrStateClkGateDist::total            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_l2esr_4.pwrStateResidencyTicks::UNDEFINED   4467555024                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_l2esr_4.pwrStateResidencyTicks::ON            0                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_l2esr_4.pwrStateResidencyTicks::CLK_GATED            0                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_l2esr_4.pwrStateResidencyTicks::SRAM_RETENTION            0                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_l2esr_4.pwrStateResidencyTicks::OFF            0                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_membnks.numPwrStateTransitions            0                       # Number of power state transitions
+system.t1000.fake_membnks.pwrStateClkGateDist::samples            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_membnks.pwrStateClkGateDist::mean          nan                       # Distribution of time spent in the clock gated state
+system.t1000.fake_membnks.pwrStateClkGateDist::stdev          nan                       # Distribution of time spent in the clock gated state
+system.t1000.fake_membnks.pwrStateClkGateDist::underflows            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_membnks.pwrStateClkGateDist::2-1e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_membnks.pwrStateClkGateDist::1e+08-2e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_membnks.pwrStateClkGateDist::2e+08-3e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_membnks.pwrStateClkGateDist::3e+08-4e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_membnks.pwrStateClkGateDist::4e+08-5e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_membnks.pwrStateClkGateDist::5e+08-6e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_membnks.pwrStateClkGateDist::6e+08-7e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_membnks.pwrStateClkGateDist::7e+08-8e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_membnks.pwrStateClkGateDist::8e+08-9e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_membnks.pwrStateClkGateDist::9e+08-1e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_membnks.pwrStateClkGateDist::1e+09-1.1e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_membnks.pwrStateClkGateDist::1.1e+09-1.2e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_membnks.pwrStateClkGateDist::1.2e+09-1.3e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_membnks.pwrStateClkGateDist::1.3e+09-1.4e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_membnks.pwrStateClkGateDist::1.4e+09-1.5e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_membnks.pwrStateClkGateDist::1.5e+09-1.6e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_membnks.pwrStateClkGateDist::1.6e+09-1.7e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_membnks.pwrStateClkGateDist::1.7e+09-1.8e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_membnks.pwrStateClkGateDist::1.8e+09-1.9e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_membnks.pwrStateClkGateDist::1.9e+09-2e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_membnks.pwrStateClkGateDist::overflows            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_membnks.pwrStateClkGateDist::min_value            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_membnks.pwrStateClkGateDist::max_value            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_membnks.pwrStateClkGateDist::total            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_membnks.pwrStateResidencyTicks::UNDEFINED   4467555024                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_membnks.pwrStateResidencyTicks::ON            0                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_membnks.pwrStateResidencyTicks::CLK_GATED            0                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_membnks.pwrStateResidencyTicks::SRAM_RETENTION            0                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_membnks.pwrStateResidencyTicks::OFF            0                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_ssi.numPwrStateTransitions            0                       # Number of power state transitions
+system.t1000.fake_ssi.pwrStateClkGateDist::samples            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_ssi.pwrStateClkGateDist::mean          nan                       # Distribution of time spent in the clock gated state
+system.t1000.fake_ssi.pwrStateClkGateDist::stdev          nan                       # Distribution of time spent in the clock gated state
+system.t1000.fake_ssi.pwrStateClkGateDist::underflows            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_ssi.pwrStateClkGateDist::2-1e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_ssi.pwrStateClkGateDist::1e+08-2e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_ssi.pwrStateClkGateDist::2e+08-3e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_ssi.pwrStateClkGateDist::3e+08-4e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_ssi.pwrStateClkGateDist::4e+08-5e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_ssi.pwrStateClkGateDist::5e+08-6e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_ssi.pwrStateClkGateDist::6e+08-7e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_ssi.pwrStateClkGateDist::7e+08-8e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_ssi.pwrStateClkGateDist::8e+08-9e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_ssi.pwrStateClkGateDist::9e+08-1e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_ssi.pwrStateClkGateDist::1e+09-1.1e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_ssi.pwrStateClkGateDist::1.1e+09-1.2e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_ssi.pwrStateClkGateDist::1.2e+09-1.3e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_ssi.pwrStateClkGateDist::1.3e+09-1.4e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_ssi.pwrStateClkGateDist::1.4e+09-1.5e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_ssi.pwrStateClkGateDist::1.5e+09-1.6e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_ssi.pwrStateClkGateDist::1.6e+09-1.7e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_ssi.pwrStateClkGateDist::1.7e+09-1.8e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_ssi.pwrStateClkGateDist::1.8e+09-1.9e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_ssi.pwrStateClkGateDist::1.9e+09-2e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_ssi.pwrStateClkGateDist::overflows            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_ssi.pwrStateClkGateDist::min_value            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_ssi.pwrStateClkGateDist::max_value            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_ssi.pwrStateClkGateDist::total            0                       # Distribution of time spent in the clock gated state
+system.t1000.fake_ssi.pwrStateResidencyTicks::UNDEFINED   4467555024                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_ssi.pwrStateResidencyTicks::ON            0                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_ssi.pwrStateResidencyTicks::CLK_GATED            0                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_ssi.pwrStateResidencyTicks::SRAM_RETENTION            0                       # Cumulative time (in ticks) in various power states
+system.t1000.fake_ssi.pwrStateResidencyTicks::OFF            0                       # Cumulative time (in ticks) in various power states
+system.t1000.htod.numPwrStateTransitions            0                       # Number of power state transitions
+system.t1000.htod.pwrStateClkGateDist::samples            0                       # Distribution of time spent in the clock gated state
+system.t1000.htod.pwrStateClkGateDist::mean          nan                       # Distribution of time spent in the clock gated state
+system.t1000.htod.pwrStateClkGateDist::stdev          nan                       # Distribution of time spent in the clock gated state
+system.t1000.htod.pwrStateClkGateDist::underflows            0                       # Distribution of time spent in the clock gated state
+system.t1000.htod.pwrStateClkGateDist::2-1e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.htod.pwrStateClkGateDist::1e+08-2e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.htod.pwrStateClkGateDist::2e+08-3e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.htod.pwrStateClkGateDist::3e+08-4e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.htod.pwrStateClkGateDist::4e+08-5e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.htod.pwrStateClkGateDist::5e+08-6e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.htod.pwrStateClkGateDist::6e+08-7e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.htod.pwrStateClkGateDist::7e+08-8e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.htod.pwrStateClkGateDist::8e+08-9e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.htod.pwrStateClkGateDist::9e+08-1e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.htod.pwrStateClkGateDist::1e+09-1.1e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.htod.pwrStateClkGateDist::1.1e+09-1.2e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.htod.pwrStateClkGateDist::1.2e+09-1.3e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.htod.pwrStateClkGateDist::1.3e+09-1.4e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.htod.pwrStateClkGateDist::1.4e+09-1.5e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.htod.pwrStateClkGateDist::1.5e+09-1.6e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.htod.pwrStateClkGateDist::1.6e+09-1.7e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.htod.pwrStateClkGateDist::1.7e+09-1.8e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.htod.pwrStateClkGateDist::1.8e+09-1.9e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.htod.pwrStateClkGateDist::1.9e+09-2e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.htod.pwrStateClkGateDist::overflows            0                       # Distribution of time spent in the clock gated state
+system.t1000.htod.pwrStateClkGateDist::min_value            0                       # Distribution of time spent in the clock gated state
+system.t1000.htod.pwrStateClkGateDist::max_value            0                       # Distribution of time spent in the clock gated state
+system.t1000.htod.pwrStateClkGateDist::total            0                       # Distribution of time spent in the clock gated state
+system.t1000.htod.pwrStateResidencyTicks::UNDEFINED   4467555024                       # Cumulative time (in ticks) in various power states
+system.t1000.htod.pwrStateResidencyTicks::ON            0                       # Cumulative time (in ticks) in various power states
+system.t1000.htod.pwrStateResidencyTicks::CLK_GATED            0                       # Cumulative time (in ticks) in various power states
+system.t1000.htod.pwrStateResidencyTicks::SRAM_RETENTION            0                       # Cumulative time (in ticks) in various power states
+system.t1000.htod.pwrStateResidencyTicks::OFF            0                       # Cumulative time (in ticks) in various power states
+system.t1000.hvuart.numPwrStateTransitions            0                       # Number of power state transitions
+system.t1000.hvuart.pwrStateClkGateDist::samples            0                       # Distribution of time spent in the clock gated state
+system.t1000.hvuart.pwrStateClkGateDist::mean          nan                       # Distribution of time spent in the clock gated state
+system.t1000.hvuart.pwrStateClkGateDist::stdev          nan                       # Distribution of time spent in the clock gated state
+system.t1000.hvuart.pwrStateClkGateDist::underflows            0                       # Distribution of time spent in the clock gated state
+system.t1000.hvuart.pwrStateClkGateDist::2-1e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.hvuart.pwrStateClkGateDist::1e+08-2e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.hvuart.pwrStateClkGateDist::2e+08-3e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.hvuart.pwrStateClkGateDist::3e+08-4e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.hvuart.pwrStateClkGateDist::4e+08-5e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.hvuart.pwrStateClkGateDist::5e+08-6e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.hvuart.pwrStateClkGateDist::6e+08-7e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.hvuart.pwrStateClkGateDist::7e+08-8e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.hvuart.pwrStateClkGateDist::8e+08-9e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.hvuart.pwrStateClkGateDist::9e+08-1e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.hvuart.pwrStateClkGateDist::1e+09-1.1e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.hvuart.pwrStateClkGateDist::1.1e+09-1.2e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.hvuart.pwrStateClkGateDist::1.2e+09-1.3e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.hvuart.pwrStateClkGateDist::1.3e+09-1.4e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.hvuart.pwrStateClkGateDist::1.4e+09-1.5e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.hvuart.pwrStateClkGateDist::1.5e+09-1.6e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.hvuart.pwrStateClkGateDist::1.6e+09-1.7e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.hvuart.pwrStateClkGateDist::1.7e+09-1.8e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.hvuart.pwrStateClkGateDist::1.8e+09-1.9e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.hvuart.pwrStateClkGateDist::1.9e+09-2e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.hvuart.pwrStateClkGateDist::overflows            0                       # Distribution of time spent in the clock gated state
+system.t1000.hvuart.pwrStateClkGateDist::min_value            0                       # Distribution of time spent in the clock gated state
+system.t1000.hvuart.pwrStateClkGateDist::max_value            0                       # Distribution of time spent in the clock gated state
+system.t1000.hvuart.pwrStateClkGateDist::total            0                       # Distribution of time spent in the clock gated state
+system.t1000.hvuart.pwrStateResidencyTicks::UNDEFINED   4467555024                       # Cumulative time (in ticks) in various power states
+system.t1000.hvuart.pwrStateResidencyTicks::ON            0                       # Cumulative time (in ticks) in various power states
+system.t1000.hvuart.pwrStateResidencyTicks::CLK_GATED            0                       # Cumulative time (in ticks) in various power states
+system.t1000.hvuart.pwrStateResidencyTicks::SRAM_RETENTION            0                       # Cumulative time (in ticks) in various power states
+system.t1000.hvuart.pwrStateResidencyTicks::OFF            0                       # Cumulative time (in ticks) in various power states
+system.t1000.iob.numPwrStateTransitions             0                       # Number of power state transitions
+system.t1000.iob.pwrStateClkGateDist::samples            0                       # Distribution of time spent in the clock gated state
+system.t1000.iob.pwrStateClkGateDist::mean          nan                       # Distribution of time spent in the clock gated state
+system.t1000.iob.pwrStateClkGateDist::stdev          nan                       # Distribution of time spent in the clock gated state
+system.t1000.iob.pwrStateClkGateDist::underflows            0                       # Distribution of time spent in the clock gated state
+system.t1000.iob.pwrStateClkGateDist::2-1e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.iob.pwrStateClkGateDist::1e+08-2e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.iob.pwrStateClkGateDist::2e+08-3e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.iob.pwrStateClkGateDist::3e+08-4e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.iob.pwrStateClkGateDist::4e+08-5e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.iob.pwrStateClkGateDist::5e+08-6e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.iob.pwrStateClkGateDist::6e+08-7e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.iob.pwrStateClkGateDist::7e+08-8e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.iob.pwrStateClkGateDist::8e+08-9e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.iob.pwrStateClkGateDist::9e+08-1e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.iob.pwrStateClkGateDist::1e+09-1.1e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.iob.pwrStateClkGateDist::1.1e+09-1.2e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.iob.pwrStateClkGateDist::1.2e+09-1.3e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.iob.pwrStateClkGateDist::1.3e+09-1.4e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.iob.pwrStateClkGateDist::1.4e+09-1.5e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.iob.pwrStateClkGateDist::1.5e+09-1.6e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.iob.pwrStateClkGateDist::1.6e+09-1.7e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.iob.pwrStateClkGateDist::1.7e+09-1.8e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.iob.pwrStateClkGateDist::1.8e+09-1.9e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.iob.pwrStateClkGateDist::1.9e+09-2e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.iob.pwrStateClkGateDist::overflows            0                       # Distribution of time spent in the clock gated state
+system.t1000.iob.pwrStateClkGateDist::min_value            0                       # Distribution of time spent in the clock gated state
+system.t1000.iob.pwrStateClkGateDist::max_value            0                       # Distribution of time spent in the clock gated state
+system.t1000.iob.pwrStateClkGateDist::total            0                       # Distribution of time spent in the clock gated state
+system.t1000.iob.pwrStateResidencyTicks::UNDEFINED   4467555024                       # Cumulative time (in ticks) in various power states
+system.t1000.iob.pwrStateResidencyTicks::ON            0                       # Cumulative time (in ticks) in various power states
+system.t1000.iob.pwrStateResidencyTicks::CLK_GATED            0                       # Cumulative time (in ticks) in various power states
+system.t1000.iob.pwrStateResidencyTicks::SRAM_RETENTION            0                       # Cumulative time (in ticks) in various power states
+system.t1000.iob.pwrStateResidencyTicks::OFF            0                       # Cumulative time (in ticks) in various power states
+system.t1000.puart0.numPwrStateTransitions            0                       # Number of power state transitions
+system.t1000.puart0.pwrStateClkGateDist::samples            0                       # Distribution of time spent in the clock gated state
+system.t1000.puart0.pwrStateClkGateDist::mean          nan                       # Distribution of time spent in the clock gated state
+system.t1000.puart0.pwrStateClkGateDist::stdev          nan                       # Distribution of time spent in the clock gated state
+system.t1000.puart0.pwrStateClkGateDist::underflows            0                       # Distribution of time spent in the clock gated state
+system.t1000.puart0.pwrStateClkGateDist::2-1e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.puart0.pwrStateClkGateDist::1e+08-2e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.puart0.pwrStateClkGateDist::2e+08-3e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.puart0.pwrStateClkGateDist::3e+08-4e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.puart0.pwrStateClkGateDist::4e+08-5e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.puart0.pwrStateClkGateDist::5e+08-6e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.puart0.pwrStateClkGateDist::6e+08-7e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.puart0.pwrStateClkGateDist::7e+08-8e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.puart0.pwrStateClkGateDist::8e+08-9e+08            0                       # Distribution of time spent in the clock gated state
+system.t1000.puart0.pwrStateClkGateDist::9e+08-1e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.puart0.pwrStateClkGateDist::1e+09-1.1e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.puart0.pwrStateClkGateDist::1.1e+09-1.2e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.puart0.pwrStateClkGateDist::1.2e+09-1.3e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.puart0.pwrStateClkGateDist::1.3e+09-1.4e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.puart0.pwrStateClkGateDist::1.4e+09-1.5e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.puart0.pwrStateClkGateDist::1.5e+09-1.6e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.puart0.pwrStateClkGateDist::1.6e+09-1.7e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.puart0.pwrStateClkGateDist::1.7e+09-1.8e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.puart0.pwrStateClkGateDist::1.8e+09-1.9e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.puart0.pwrStateClkGateDist::1.9e+09-2e+09            0                       # Distribution of time spent in the clock gated state
+system.t1000.puart0.pwrStateClkGateDist::overflows            0                       # Distribution of time spent in the clock gated state
+system.t1000.puart0.pwrStateClkGateDist::min_value            0                       # Distribution of time spent in the clock gated state
+system.t1000.puart0.pwrStateClkGateDist::max_value            0                       # Distribution of time spent in the clock gated state
+system.t1000.puart0.pwrStateClkGateDist::total            0                       # Distribution of time spent in the clock gated state
+system.t1000.puart0.pwrStateResidencyTicks::UNDEFINED   4467555024                       # Cumulative time (in ticks) in various power states
+system.t1000.puart0.pwrStateResidencyTicks::ON            0                       # Cumulative time (in ticks) in various power states
+system.t1000.puart0.pwrStateResidencyTicks::CLK_GATED            0                       # Cumulative time (in ticks) in various power states
+system.t1000.puart0.pwrStateResidencyTicks::SRAM_RETENTION            0                       # Cumulative time (in ticks) in various power states
+system.t1000.puart0.pwrStateResidencyTicks::OFF            0                       # Cumulative time (in ticks) in various power states
 
 ---------- End Simulation Statistics   ----------