x86: fix vgf2p8affine*qb insns

The affine transformations are not commutative (the two source operands
have entirely different meaning).

Also the nonimmediate_operand predicate can better be vector_operand.

From-SVN: r272783

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 6f028eee3cce6f39dc1c1ac4beadcfc6b1417d3b..f30fedc89e76aa4990eed27567e9f2ca43ac0967 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2019-06-28  Jan Beulich  <jbeulich@suse.com>
+
+       * config/i386/sse.md (vgf2p8affineinvqb_<mode><mask_name>,
+       vgf2p8affineqb_<mode><mask_name>): Drop % constraint modifier.
+       Use vector_operand.
+
 2019-06-28  Claudiu Zissulescu  <claziss@synopsys.com>
 
        * config/arc/arc.c (arc_rtx_costs): All short instructions are

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 154681786e0e0f74f9647d7be3f14200c1be8f32..713e3c894197e9913599841e5894baa89216df1a 100644 (file)
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -22112,8 +22112,8 @@
 (define_insn "vgf2p8affineinvqb_<mode><mask_name>"
   [(set (match_operand:VI1_AVX512F 0 "register_operand" "=x,x,v")
        (unspec:VI1_AVX512F
-         [(match_operand:VI1_AVX512F 1 "register_operand" "%0,x,v")
-          (match_operand:VI1_AVX512F 2 "nonimmediate_operand" "xBm,xm,vm")
+         [(match_operand:VI1_AVX512F 1 "register_operand" "0,x,v")
+          (match_operand:VI1_AVX512F 2 "vector_operand" "xBm,xm,vm")
           (match_operand:QI 3 "const_0_to_255_operand" "n,n,n")]
          UNSPEC_GF2P8AFFINEINV))]
   "TARGET_GFNI"
@@ -22130,8 +22130,8 @@
 (define_insn "vgf2p8affineqb_<mode><mask_name>"
   [(set (match_operand:VI1_AVX512F 0 "register_operand" "=x,x,v")
        (unspec:VI1_AVX512F
-         [(match_operand:VI1_AVX512F 1 "register_operand" "%0,x,v")
-          (match_operand:VI1_AVX512F 2 "nonimmediate_operand" "xBm,xm,vm")
+         [(match_operand:VI1_AVX512F 1 "register_operand" "0,x,v")
+          (match_operand:VI1_AVX512F 2 "vector_operand" "xBm,xm,vm")
           (match_operand:QI 3 "const_0_to_255_operand" "n,n,n")]
          UNSPEC_GF2P8AFFINE))]
   "TARGET_GFNI"

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index a1fbb04a997719a4691cbc9a968ff039b8a461e6..a340bc4e869dae062c54841e32a447469b7d8ca7 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2019-06-28  Jan Beulich  <jbeulich@suse.com>
+
+       * gcc.target/i386/gfni-5.c: New.
+
 2019-06-28  Jan Beulich  <jbeulich@suse.com>
 
        * gcc.target/i386/cvtpd2pi: New.

diff --git a/gcc/testsuite/gcc.target/i386/gfni-5.c b/gcc/testsuite/gcc.target/i386/gfni-5.c
new file mode 100644 (file)
index 0000000..b355219
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/gfni-5.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2 -mgfni" } */
+
+typedef char __attribute__((vector_size(16))) v16qi_t;
+
+v16qi_t test16a (v16qi_t x, v16qi_t a)
+{
+  asm volatile ("" : "+m" (a));
+  return __builtin_ia32_vgf2p8affineqb_v16qi (x, a, 0);
+}
+
+v16qi_t test16b (v16qi_t x, v16qi_t a)
+{
+  asm volatile ("" : "+m" (x));
+  return __builtin_ia32_vgf2p8affineqb_v16qi (x, a, 0);
+}
+
+/* { dg-final { scan-assembler-times "gf2p8affineqb\[ \t].*\\(" 1 } } */
+/* { dg-final { scan-assembler-times "gf2p8affineqb\[ \t].*%xmm.*%xmm" 1 } } */