ruby: remove the functional copy of memory in se mode

This patch removes the functional copy of the memory that was maintained in
the se mode. Now ruby itself will provide the data.

diff --git a/configs/example/ruby_fs.py b/configs/example/ruby_fs.py
index 8d21cfb3280e3968b40c00df49da92559e395939..32ddb90bfc488e3b34603124523be478a49829b8 100644 (file)
--- a/configs/example/ruby_fs.py
+++ b/configs/example/ruby_fs.py
@@ -114,5 +114,7 @@ for (i, cpu) in enumerate(system.cpu):
         cpu.interrupts.int_master = system.piobus.slave
         cpu.interrupts.int_slave = system.piobus.master
 
+    system.ruby._cpu_ruby_ports[i].access_phys_mem = True
+
 root = Root(full_system = True, system = system)
 Simulation.run(options, root, system, FutureClass)

diff --git a/configs/example/se.py b/configs/example/se.py
index fe5524ef500b400177b375dea4f0b5c8c2aff1f2..20149cccddbd5ace9265c290b02d5abece8c7277 100644 (file)
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -187,6 +187,9 @@ if options.ruby:
         print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
         sys.exit(1)
 
+    # Set the option for physmem so that it is not allocated any space
+    system.physmem.null = True
+
     options.use_map = True
     Ruby.create_system(options, system)
     assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))

diff --git a/src/mem/ruby/system/Sequencer.py b/src/mem/ruby/system/Sequencer.py
index 9b243a8b94a4705c29fa03d548a0c75fb58f9946..68d02f53ceaa3495f94b94e8629ca5b8e8324e42 100644 (file)
--- a/src/mem/ruby/system/Sequencer.py
+++ b/src/mem/ruby/system/Sequencer.py
@@ -41,7 +41,7 @@ class RubyPort(MemObject):
     pio_port = MasterPort("Ruby_pio_port")
     using_ruby_tester = Param.Bool(False, "")
     using_network_tester = Param.Bool(False, "")
-    access_phys_mem = Param.Bool(True,
+    access_phys_mem = Param.Bool(False,
         "should the rubyport atomically update phys_mem")
     ruby_system = Param.RubySystem("")
     system = Param.System(Parent.any, "system object")
@@ -52,6 +52,7 @@ class RubyPort(MemObject):
 class RubyPortProxy(RubyPort):
     type = 'RubyPortProxy'
     cxx_header = "mem/ruby/system/RubyPortProxy.hh"
+    access_phys_mem = True
     
 class RubySequencer(RubyPort):
     type = 'RubySequencer'
@@ -67,3 +68,4 @@ class RubySequencer(RubyPort):
 class DMASequencer(RubyPort):
     type = 'DMASequencer'
     cxx_header = "mem/ruby/system/DMASequencer.hh"
+    access_phys_mem = True

diff --git a/tests/configs/memtest-ruby.py b/tests/configs/memtest-ruby.py
index 397e9f0c73975ef76802fca8c83c17134ecbd13a..a252bc8813a94517add515f85cc62bc05866c39f 100644 (file)
--- a/tests/configs/memtest-ruby.py
+++ b/tests/configs/memtest-ruby.py
@@ -79,8 +79,8 @@ options.num_cpus = nb_cores
 # system simulated
 system = System(cpu = cpus,
                 funcmem = SimpleMemory(in_addr_map = False),
-                funcbus = NoncoherentBus(),
-                physmem = SimpleMemory())
+                physmem = SimpleMemory(null = True),
+                funcbus = NoncoherentBus())
 
 Ruby.create_system(options, system)
 
@@ -100,12 +100,6 @@ for (i, ruby_port) in enumerate(system.ruby._cpu_ruby_ports):
      #
      ruby_port.deadlock_threshold = 1000000
 
-     #
-     # Ruby doesn't need the backing image of memory when running with
-     # the tester.
-     #
-     ruby_port.access_phys_mem = False
-
 # connect reference memory to funcbus
 system.funcmem.port = system.funcbus.master
 

diff --git a/tests/configs/pc-simple-timing-ruby.py b/tests/configs/pc-simple-timing-ruby.py
index 0753472bc5ef8e8e942b803c78e8d51c9b99e599..23a0bb3d0b083000c170b5aee2c0a05290665713 100644 (file)
--- a/tests/configs/pc-simple-timing-ruby.py
+++ b/tests/configs/pc-simple-timing-ruby.py
@@ -74,5 +74,8 @@ for (i, cpu) in enumerate(system.cpu):
     cpu.interrupts.int_slave = system.piobus.master
     cpu.clock = '2GHz'
 
+    # Set access_phys_mem to True for ruby port
+    system.ruby._cpu_ruby_ports[i].access_phys_mem = True
+
 root = Root(full_system = True, system = system)
 m5.ticks.setGlobalFrequency('1THz')

diff --git a/tests/configs/rubytest-ruby.py b/tests/configs/rubytest-ruby.py
index 4b5b3a19ca03e96e4b5d4ec4ebe281125c5d632f..861205accff7ff071a6c9a4d8448a661a79797cc 100644 (file)
--- a/tests/configs/rubytest-ruby.py
+++ b/tests/configs/rubytest-ruby.py
@@ -77,7 +77,7 @@ if buildEnv['PROTOCOL'] == 'MOESI_hammer':
 tester = RubyTester(check_flush = check_flush, checks_to_complete = 100,
                     wakeup_frequency = 10, num_cpus = options.num_cpus)
 
-system = System(tester = tester, physmem = SimpleMemory())
+system = System(tester = tester, physmem = SimpleMemory(null = True))
 
 Ruby.create_system(options, system)
 
@@ -104,12 +104,6 @@ for ruby_port in system.ruby._cpu_ruby_ports:
     #
     ruby_port.using_ruby_tester = True
 
-    #
-    # Ruby doesn't need the backing image of memory when running with
-    # the tester.
-    #
-    ruby_port.access_phys_mem = False
-
 # -----------------------
 # run simulation
 # -----------------------

diff --git a/tests/configs/simple-timing-ruby.py b/tests/configs/simple-timing-ruby.py
index 86869452a996736154687385ff5d325748f8d559..41b4fdb1fcd7f12d9dc2787abe5f33fcd814d848 100644 (file)
--- a/tests/configs/simple-timing-ruby.py
+++ b/tests/configs/simple-timing-ruby.py
@@ -67,7 +67,7 @@ options.l3_assoc=2
 options.num_cpus = 1
 
 cpu = TimingSimpleCPU(cpu_id=0)
-system = System(cpu = cpu, physmem = SimpleMemory())
+system = System(cpu = cpu, physmem = SimpleMemory(null = True))
 
 Ruby.create_system(options, system)