Call equiv_opt with -multiclock and -assert

diff --git a/tests/arch/anlogic/counter.ys b/tests/arch/anlogic/counter.ys
index d363ec24e017df4a0fda6c2b5391532cdb1ebe32..a6eab248cc4af4f9c21c93ee99c62e5b05719948 100644 (file)
--- a/tests/arch/anlogic/counter.ys
+++ b/tests/arch/anlogic/counter.ys
@@ -2,7 +2,7 @@ read_verilog ../common/counter.v
 hierarchy -top top
 proc
 flatten
-equiv_opt -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
+equiv_opt -assert -multiclock -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 

diff --git a/tests/arch/ecp5/counter.ys b/tests/arch/ecp5/counter.ys
index f9f60fbff69cd552e48a19f294c02f682dafd65d..e46001ffede4342a4e9dce8ebb8e903084de6946 100644 (file)
--- a/tests/arch/ecp5/counter.ys
+++ b/tests/arch/ecp5/counter.ys
@@ -2,7 +2,7 @@ read_verilog ../common/counter.v
 hierarchy -top top
 proc
 flatten
-equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
+equiv_opt -assert -multiclock -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 4 t:CCU2C

diff --git a/tests/arch/efinix/counter.ys b/tests/arch/efinix/counter.ys
index d20b8ae271fa670c9099ea806c63de4e2fe30cae..f8fb29a87b1892333b3fbc14ff1426034bc63400 100644 (file)
--- a/tests/arch/efinix/counter.ys
+++ b/tests/arch/efinix/counter.ys
@@ -2,7 +2,7 @@ read_verilog ../common/counter.v
 hierarchy -top top
 proc
 flatten
-equiv_opt -map +/efinix/cells_sim.v synth_efinix # equivalency check
+equiv_opt -assert -multiclock -map +/efinix/cells_sim.v synth_efinix # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 

diff --git a/tests/arch/gowin/counter.ys b/tests/arch/gowin/counter.ys
index 920479d44c662045abc67f35d0a53de8ca18cdf2..bdbc7ee2432ddfd74e6d3a5e95d43317b41a7063 100644 (file)
--- a/tests/arch/gowin/counter.ys
+++ b/tests/arch/gowin/counter.ys
@@ -2,7 +2,7 @@ read_verilog ../common/counter.v
 hierarchy -top top
 proc
 flatten
-equiv_opt -map +/gowin/cells_sim.v synth_gowin # equivalency check
+equiv_opt -assert -multiclock -map +/gowin/cells_sim.v synth_gowin # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 

diff --git a/tests/arch/ice40/counter.ys b/tests/arch/ice40/counter.ys
index f112eb97d8f729708533fd1558a8f188d1c1f31b..7bbc4f2c33fb4a4b0cae75d8773e77bdafb89684 100644 (file)
--- a/tests/arch/ice40/counter.ys
+++ b/tests/arch/ice40/counter.ys
@@ -2,7 +2,7 @@ read_verilog ../common/counter.v
 hierarchy -top top
 proc
 flatten
-equiv_opt -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+equiv_opt -assert -multiclock -map +/ice40/cells_sim.v synth_ice40 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 6 t:SB_CARRY