ac: add has_distributed_tess to ac_gpu_info

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index ed6e273c598f2f7e36cc947d02ed6901cafba0cf..a3f1afe1f0455965ec3186eaee950a6d3f9b3e57 100644 (file)
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -447,6 +447,9 @@ bool ac_query_gpu_info(int fd, void *dev_p,
         */
        info->has_clear_state = info->chip_class >= GFX7;
 
+       info->has_distributed_tess = info->chip_class >= GFX8 &&
+                                    info->max_se >= 2;
+
        /* Get the number of good compute units. */
        info->num_good_compute_units = 0;
        for (i = 0; i < info->max_se; i++)

diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index 69bac7252bf4927c2ac75dbc49224552ba2a0135..9ce1650c03c25376d1dbad11231d7b1a01993fd0 100644 (file)
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -59,6 +59,7 @@ struct radeon_info {
        uint32_t                    clock_crystal_freq;
        uint32_t                    tcc_cache_line_size;
        bool                        has_clear_state;
+       bool                        has_distributed_tess;
 
        /* There are 2 display DCC codepaths, because display expects unaligned DCC. */
        /* Disable RB and pipe alignment to skip the retile blit. (1 RB chips only) */

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index ca484fcc0fc28c988077c977ec7cb919f041e584..ad5c104f44fa9e74802c23439903f9b0f65edb8f 100644 (file)
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -2005,9 +2005,6 @@ VkResult radv_CreateDevice(
 
        device->tess_offchip_block_dw_size =
                device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
-       device->has_distributed_tess =
-               device->physical_device->rad_info.chip_class >= GFX8 &&
-               device->physical_device->rad_info.max_se >= 2;
 
        if (getenv("RADV_TRACE_FILE")) {
                const char *filename = getenv("RADV_TRACE_FILE");

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index e43b77b192e6104462e37e2d7f5aa08e8280fec8..584dddb48dfd05a00871f6f9f569800cfbe6eebd 100644 (file)
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -2010,7 +2010,7 @@ calculate_tess_state(struct radv_pipeline *pipeline,
        else
                topology = V_028B6C_OUTPUT_TRIANGLE_CW;
 
-       if (pipeline->device->has_distributed_tess) {
+       if (pipeline->device->physical_device->rad_info.has_distributed_tess) {
                if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
                    pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
                        distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
@@ -4378,7 +4378,7 @@ radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
                    radv_pipeline_has_gs(pipeline))
                        ia_multi_vgt_param.partial_vs_wave = true;
                /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
-               if (device->has_distributed_tess) {
+               if (device->physical_device->rad_info.has_distributed_tess) {
                        if (radv_pipeline_has_gs(pipeline)) {
                                if (device->physical_device->rad_info.chip_class <= GFX8)
                                        ia_multi_vgt_param.partial_es_wave = true;

diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 39d349b723c5e3ca97140597eaf6a16e89fb03d1..287c2abfa3fa27cd637fb822ef8174947dbff00e 100644 (file)
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -704,7 +704,6 @@ struct radv_device {
        struct radeon_cmdbuf *empty_cs[RADV_MAX_QUEUE_FAMILIES];
 
        bool always_use_syncobj;
-       bool has_distributed_tess;
        bool pbb_allowed;
        bool dfsm_allowed;
        uint32_t tess_offchip_block_dw_size;

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index 21e785dd44fa75aa210bf296432cb03f8f58c367..b6fce0640f4038d28890bf6dabee4cbfd7dbbae5 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -1109,10 +1109,6 @@ radeonsi_screen_create_impl(struct radeon_winsys *ws,
                        S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
        }
 
-       sscreen->has_distributed_tess =
-               sscreen->info.chip_class >= GFX8 &&
-               sscreen->info.max_se >= 2;
-
        sscreen->has_draw_indirect_multi =
                (sscreen->info.family >= CHIP_POLARIS10) ||
                (sscreen->info.chip_class == GFX8 &&

diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index 4630fff73571ea6aa3f2a4982457f739f072897d..6b0b5d3e20d66f6100f264c71974d41b3dd836bf 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -491,7 +491,6 @@ struct si_screen {
        unsigned                        eqaa_force_coverage_samples;
        unsigned                        eqaa_force_z_samples;
        unsigned                        eqaa_force_color_samples;
-       bool                            has_distributed_tess;
        bool                            has_draw_indirect_multi;
        bool                            has_out_of_order_rast;
        bool                            assume_no_z_fights;

diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index 118d87e4734e3b93748a32e0a788ea136847e26a..dd4b13fe97f9e3b44572eef6ceff23115a895fa1 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -175,7 +175,7 @@ static void si_emit_derived_tess_state(struct si_context *sctx,
        /* When distributed tessellation is unsupported, switch between SEs
         * at a higher frequency to compensate for it.
         */
-       if (!sctx->screen->has_distributed_tess && sctx->screen->info.max_se > 1)
+       if (!sctx->screen->info.has_distributed_tess && sctx->screen->info.max_se > 1)
                *num_patches = MIN2(*num_patches, 16); /* recommended */
 
        /* Make sure that vector lanes are reasonably occupied. It probably
@@ -363,7 +363,7 @@ si_get_init_multi_vgt_param(struct si_screen *sscreen,
                        partial_vs_wave = true;
 
                /* Needed for 028B6C_DISTRIBUTION_MODE != 0. (implies >= GFX8) */
-               if (sscreen->has_distributed_tess) {
+               if (sscreen->info.has_distributed_tess) {
                        if (key->u.uses_gs) {
                                if (sscreen->info.chip_class == GFX8)
                                        partial_es_wave = true;

diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 8934e06ed9a76cae101402fe6741090ee0ad6fce..003d116e8eb4711f0f75d18611bc77105cba7e7a 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -382,7 +382,7 @@ static void si_set_tesseval_regs(struct si_screen *sscreen,
        else
                topology = V_028B6C_OUTPUT_TRIANGLE_CW;
 
-       if (sscreen->has_distributed_tess) {
+       if (sscreen->info.has_distributed_tess) {
                if (sscreen->info.family == CHIP_FIJI ||
                    sscreen->info.family >= CHIP_POLARIS10)
                        distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;