const char *cstr(RTLIL::SigSpec sig)
{
- sig.optimize();
log_assert(sig.size() == 1);
if (sig.chunks().at(0).wire == NULL)
}
for (auto &it : net_join_db) {
RTLIL::SigSpec sig = it.first;
- sig.optimize();
log_assert(sig.size() == 1);
if (sig.chunks().at(0).wire == NULL) {
if (sig.chunks().at(0).data.bits.at(0) != RTLIL::State::S0 && sig.chunks().at(0).data.bits.at(0) != RTLIL::State::S1)
static std::string netname(std::set<std::string> &conntypes_code, std::set<std::string> &celltypes_code, std::set<std::string> &constcells_code, RTLIL::SigSpec sig)
{
- sig.optimize();
-
if (sig.chunks().size() != 1)
error:
log_error("Can't export composite or non-word-wide signal %s.\n", log_signal(sig));
bool is_reg_wire(RTLIL::SigSpec sig, std::string ®_name)
{
- sig.optimize();
if (sig.chunks().size() != 1 || sig.chunks()[0].wire == NULL)
return false;
if (reg_wires.count(sig.chunks()[0].wire->name) == 0)
if (sig.size() != 1 || sig.is_fully_const())
goto no_special_reg_name;
- sig.optimize();
RTLIL::Wire *wire = sig.chunks()[0].wire;
if (wire->name[0] != '\\')
continue;
RTLIL::SigSpec sig = cell->connections["\\Q"];
- sig.optimize();
if (sig.chunks().size() == 1 && sig.chunks()[0].wire)
for (int i = 0; i < sig.chunks()[0].width; i++)
proc->syncs.push_back(sync);
assert(init_lvalue.size() == init_rvalue.size());
- init_lvalue.optimize();
- init_rvalue.optimize();
int offset = 0;
for (size_t i = 0; i < init_lvalue.chunks().size(); i++) {
// create new temporary signals
RTLIL::SigSpec new_temp_signal(RTLIL::SigSpec sig)
{
- sig.optimize();
std::vector<RTLIL::SigChunk> chunks = sig.chunks();
for (int i = 0; i < SIZE(chunks); i++)
lvalue.remove2(initSyncSignals, &rvalue);
}
assert(lvalue.size() == rvalue.size());
- lvalue.optimize();
- rvalue.optimize();
int offset = 0;
for (size_t i = 0; i < lvalue.chunks().size(); i++) {
if (ast->type == AST_ASSIGN_EQ) {
subst_rvalue_from.remove2(unmapped_lvalue, &subst_rvalue_to);
subst_rvalue_from.append(unmapped_lvalue);
- subst_rvalue_from.optimize();
subst_rvalue_to.append(rvalue);
- subst_rvalue_to.optimize();
}
removeSignalFromCaseTree(lvalue, current_case);
subst_lvalue_from.remove2(this_case_eq_lvalue, &subst_lvalue_to);
subst_lvalue_from.append(this_case_eq_lvalue);
- subst_lvalue_from.optimize();
subst_lvalue_to.append(this_case_eq_ltemp);
- subst_lvalue_to.optimize();
RTLIL::CaseRule *backup_case = current_case;
current_case = new RTLIL::CaseRule;
subst_rvalue_from.remove2(this_case_eq_lvalue, &subst_rvalue_to);
subst_rvalue_from.append(this_case_eq_lvalue);
- subst_rvalue_from.optimize();
subst_rvalue_to.append(this_case_eq_ltemp);
- subst_rvalue_to.optimize();
this_case_eq_lvalue.replace(subst_lvalue_from, subst_lvalue_to);
removeSignalFromCaseTree(this_case_eq_lvalue, current_case);
width = sig.size();
if (width > 0) {
std::vector<RTLIL::State> pattern(width);
- sig.optimize();
for (int i = 0; i < width; i++) {
RTLIL::SigSpec s = sig.extract(i, 1);
- s.optimize();
assert(s.chunks().size() == 1);
if (s.chunks()[0].wire == NULL && s.chunks()[0].data.bits[0] <= RTLIL::State::S1)
pattern[i] = s.chunks()[0].data.bits[0];
bits_t sig2bits(RTLIL::SigSpec sig)
{
- sig.optimize();
assert(sig.is_fully_const());
assert(sig.chunks().size() == 1);
bits_t bits = sig.chunks()[0].data.bits;
void RTLIL::Module::optimize()
{
- for (auto &it : cells)
- it.second->optimize();
- for (auto &it : processes)
- it.second->optimize();
- for (auto &it : connections) {
- it.first.optimize();
- it.second.optimize();
- }
}
void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
size = 0;
}
-void RTLIL::Cell::optimize()
-{
- for (auto &it : connections)
- it.second.optimize();
-}
-
void RTLIL::Cell::check()
{
InternalCellChecker checker(NULL, this);
return bits_.empty();
}
-void RTLIL::SigSpec::optimize()
-{
-#if 0
- pack();
- std::vector<RTLIL::SigChunk> new_chunks;
- for (auto &c : chunks_)
- if (new_chunks.size() == 0) {
- new_chunks.push_back(c);
- } else {
- RTLIL::SigChunk &cc = new_chunks.back();
- if (c.wire == NULL && cc.wire == NULL)
- cc.data.bits.insert(cc.data.bits.end(), c.data.bits.begin(), c.data.bits.end());
- if (c.wire == cc.wire && (c.wire == NULL || cc.offset + cc.width == c.offset))
- cc.width += c.width;
- else
- new_chunks.push_back(c);
- }
- chunks_.swap(new_chunks);
- check();
-#endif
-}
-
-RTLIL::SigSpec RTLIL::SigSpec::optimized() const
-{
-#if 0
- pack();
- RTLIL::SigSpec ret = *this;
- ret.optimize();
- return ret;
-#else
- return *this;
-#endif
-}
-
void RTLIL::SigSpec::sort()
{
unpack();
while (width_ < width)
append(padding);
}
-
- optimize();
}
void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
append(padding);
}
- optimize();
}
void RTLIL::SigSpec::check() const
return width_ < other.width_;
RTLIL::SigSpec a = *this, b = other;
- a.optimize();
- b.optimize();
if (a.chunks_.size() != b.chunks_.size())
return a.chunks_.size() < b.chunks_.size();
return false;
RTLIL::SigSpec a = *this, b = other;
- a.optimize();
- b.optimize();
if (a.chunks_.size() != b.chunks_.size())
return false;
bool RTLIL::SigSpec::as_bool() const
{
pack();
- assert(is_fully_const());
- SigSpec sig = *this;
- sig.optimize();
- if (sig.width_)
- return sig.chunks_[0].data.as_bool();
+ assert(is_fully_const() && SIZE(chunks_) <= 1);
+ if (width_)
+ return chunks_[0].data.as_bool();
return false;
}
int RTLIL::SigSpec::as_int() const
{
pack();
- assert(is_fully_const());
- SigSpec sig = *this;
- sig.optimize();
- if (sig.width_)
- return sig.chunks_[0].data.as_int();
+ assert(is_fully_const() && SIZE(chunks_) <= 1);
+ if (width_)
+ return chunks_[0].data.as_int();
return 0;
}
RTLIL::Const RTLIL::SigSpec::as_const() const
{
pack();
- assert(is_fully_const());
- SigSpec sig = *this;
- sig.optimize();
- if (sig.width_)
- return sig.chunks_[0].data;
+ assert(is_fully_const() && SIZE(chunks_) <= 1);
+ if (width_)
+ return chunks_[0].data;
return RTLIL::Const();
}
delete *it;
}
-void RTLIL::CaseRule::optimize()
-{
- for (auto it : switches)
- it->optimize();
- for (auto &it : compare)
- it.optimize();
- for (auto &it : actions) {
- it.first.optimize();
- it.second.optimize();
- }
-}
-
RTLIL::CaseRule *RTLIL::CaseRule::clone() const
{
RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
delete *it;
}
-void RTLIL::SwitchRule::optimize()
-{
- signal.optimize();
- for (auto it : cases)
- it->optimize();
-}
-
RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
{
RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
}
-void RTLIL::SyncRule::optimize()
-{
- signal.optimize();
- for (auto &it : actions) {
- it.first.optimize();
- it.second.optimize();
- }
-}
-
RTLIL::SyncRule *RTLIL::SyncRule::clone() const
{
RTLIL::SyncRule *new_syncrule = new RTLIL::SyncRule;
delete *it;
}
-void RTLIL::Process::optimize()
-{
- root_case.optimize();
- for (auto it : syncs)
- it->optimize();
-}
-
RTLIL::Process *RTLIL::Process::clone() const
{
RTLIL::Process *new_proc = new RTLIL::Process;
std::map<RTLIL::IdString, RTLIL::SigSpec> connections;
std::map<RTLIL::IdString, RTLIL::Const> parameters;
RTLIL_ATTRIBUTE_MEMBERS
- void optimize();
void check();
template<typename T> void rewrite_sigspecs(T functor);
inline RTLIL::SigSpecIterator begin() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = 0; return it; }
inline RTLIL::SigSpecIterator end() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = width_; return it; }
- void optimize();
- RTLIL::SigSpec optimized() const;
-
void sort();
void sort_and_unify();
RTLIL_ATTRIBUTE_MEMBERS
std::vector<RTLIL::CaseRule*> cases;
~SwitchRule();
- void optimize();
template<typename T> void rewrite_sigspecs(T functor);
RTLIL::SwitchRule *clone() const;
RTLIL::SyncType type;
RTLIL::SigSpec signal;
std::vector<RTLIL::SigSig> actions;
- void optimize();
template<typename T> void rewrite_sigspecs(T functor);
RTLIL::SyncRule *clone() const;
RTLIL::CaseRule root_case;
std::vector<RTLIL::SyncRule*> syncs;
~Process();
- void optimize();
template<typename T> void rewrite_sigspecs(T functor);
RTLIL::Process *clone() const;
goto continue_without_read;
}
- input_sig.optimize();
- output_sig.optimize();
-
RTLIL::Cell *cell = new RTLIL::Cell;
cell->name = NEW_ID;
cell->type = "$lut";
RTLIL::SigSpec bits;
for (int i = 0; i < c.width; i++)
bits.append(worker.next_bit());
- bits.optimize();
module->connections.push_back(RTLIL::SigSig(c, bits));
}
}
std::string gen_signode_simple(RTLIL::SigSpec sig, bool range_check = true)
{
- sig.optimize();
-
if (sig.chunks().size() == 0) {
fprintf(f, "v%d [ label=\"\" ];\n", single_idx_count);
return stringf("v%d", single_idx_count++);
if (net.empty())
{
std::string label_string;
- sig.optimize();
int pos = sig.size()-1;
int idx = single_idx_count++;
for (int i = int(sig.chunks().size())-1; i >= 0; i--) {
module->add(cell);
}
- new_sig.optimize();
sliced_signals_cache[sig] = new_sig;
return new_sig;
module->add(cell);
}
- new_sig.optimize();
spliced_signals_cache[sig] = new_sig;
log(" Created spliced signal: %s -> %s\n", log_signal(sig), log_signal(new_sig));
if (!ct.cell_output(c.second->type, p.first))
continue;
- RTLIL::SigSpec sig = p.second.optimized();
+ RTLIL::SigSpec sig = p.second;
for (auto &chunk : sig.chunks()) {
if (chunk.wire == NULL)
continue;
eq_sig_a.append(ctrl_in.extract(j, 1));
eq_sig_b.append(RTLIL::SigSpec(pattern.bits[j]));
}
- eq_sig_a.optimize();
- eq_sig_b.optimize();
for (int in_state : it.second)
if (fullstate_cache.count(in_state) == 0)
or_sig.append(RTLIL::SigSpec(state_onehot, in_state));
- or_sig.optimize();
if (or_sig.size() == 0)
continue;
sig_a.append(RTLIL::SigSpec(state_wire, j));
sig_b.append(RTLIL::SigSpec(state.bits[j]));
}
- sig_a.optimize();
- sig_b.optimize();
if (sig_b == RTLIL::SigSpec(RTLIL::State::S1))
{
mem->parameters["\\SIZE"] = RTLIL::Const(memory->size);
mem->parameters["\\ABITS"] = RTLIL::Const(addr_bits);
- sig_wr_clk_enable.optimize();
- sig_wr_clk_polarity.optimize();
-
assert(sig_wr_clk.size() == wr_ports);
assert(sig_wr_clk_enable.size() == wr_ports && sig_wr_clk_enable.is_fully_const());
assert(sig_wr_clk_polarity.size() == wr_ports && sig_wr_clk_polarity.is_fully_const());
mem->connections["\\WR_DATA"] = sig_wr_data;
mem->connections["\\WR_EN"] = sig_wr_en;
- sig_rd_clk_enable.optimize();
- sig_rd_clk_polarity.optimize();
- sig_rd_transparent.optimize();
-
assert(sig_rd_clk.size() == rd_ports);
assert(sig_rd_clk_enable.size() == rd_ports && sig_rd_clk_enable.is_fully_const());
assert(sig_rd_clk_polarity.size() == rd_ports && sig_rd_clk_polarity.is_fully_const());
replaced_this_bit:;
}
- sig.optimize();
return true;
}
merged_en.replace(k, cell_en.extract(k, 1));
merged_data.replace(k, cell_data.extract(k, 1));
}
- merged_en.optimize();
- merged_data.optimize();
}
// Connect the new EN and DATA signals and remove the old write port.
new_conn.second.append_bit(s2[i]);
}
if (new_conn.first.size() > 0) {
- new_conn.first.optimize();
- new_conn.second.optimize();
used_signals.add(new_conn.first);
used_signals.add(new_conn.second);
module->connections.push_back(new_conn);
}
if (new_a.size() < a.size() || new_b.size() < b.size()) {
- new_a.optimize();
- new_b.optimize();
cell->connections["\\A"] = new_a;
cell->connections["\\B"] = new_b;
cell->parameters["\\A_WIDTH"] = new_a.size();
ce.assign_map.apply(rstval);
ce.assign_map.apply(sig);
- insig.optimize();
- rstval.optimize();
- sig.optimize();
-
if (rstval == sig) {
rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size());
sync_level = NULL;
assert(rule.compare.size() == 0);
while (1) {
- sig.optimize();
RTLIL::SigSpec tmp = sig;
for (auto &it : rule.actions)
tmp.replace(it.first, it.second);
RTLIL::SigSpec lhs = action.first;
RTLIL::SigSpec rhs = action.second;
- lhs.optimize();
proc_get_const(rhs, proc->root_case);
if (!rhs.is_fully_const())
return;
}
- inputs.optimize();
-
ConstEval ce1(mod1), ce2(mod2);
ce1.set(mod1_inputs, inputs.as_const());
ce2.set(mod2_inputs, inputs.as_const());
RTLIL::SigSpec signal, value, undef;
if (!RTLIL::SigSpec::parse_sel(signal, design, module, it))
log_cmd_error("Failed to parse show expression `%s'.\n", it.c_str());
- signal.optimize();
value = signal;
if (set_undef) {
while (!ce.eval(value, undef)) {
std::vector<RTLIL::SigBit> bucket_sigbits;
for (int idx : bucket)
bucket_sigbits.push_back(out_bits[idx]);
- log("%s Trying to shatter bucket with %d signals: %s\n", indt, int(bucket.size()), log_signal(RTLIL::SigSpec(bucket_sigbits).optimized()));
+ log("%s Trying to shatter bucket with %d signals: %s\n", indt, int(bucket.size()), log_signal(bucket_sigbits));
}
std::vector<int> sat_set_list, sat_clr_list;
std::vector<RTLIL::SigBit> r_sigbits;
for (int idx : r)
r_sigbits.push_back(out_bits[idx]);
- log(" Found group of %d equivialent signals: %s\n", int(r.size()), log_signal(RTLIL::SigSpec(r_sigbits).optimized()));
+ log(" Found group of %d equivialent signals: %s\n", int(r.size()), log_signal(r_sigbits));
}
std::vector<int> undef_slaves;
found_selected_wire:
log(" Finding reduced input cone for signal batch %s%c\n",
- log_signal(RTLIL::SigSpec(std::vector<RTLIL::SigBit>(batch.begin(), batch.end())).optimized()), verbose_level ? ':' : '.');
+ log_signal(batch), verbose_level ? ':' : '.');
FindReducedInputs infinder(sigmap, drivers);
for (auto &bit : batch) {
continue;
if (bucket.first.size() == 0) {
- log(" Finding const values for bucket %s%c\n", log_signal(RTLIL::SigSpec(bucket.second).optimized()), verbose_level ? ':' : '.');
+ log(" Finding const values for bucket %s%c\n", log_signal(bucket.second), verbose_level ? ':' : '.');
PerformReduction worker(sigmap, drivers, inv_pairs, bucket.second, bucket.first.size());
for (size_t idx = 0; idx < bucket.second.size(); idx++)
worker.analyze_const(equiv, idx);
} else {
- log(" Trying to shatter bucket %s%c\n", log_signal(RTLIL::SigSpec(bucket.second).optimized()), verbose_level ? ':' : '.');
+ log(" Trying to shatter bucket %s%c\n", log_signal(bucket.second), verbose_level ? ':' : '.');
PerformReduction worker(sigmap, drivers, inv_pairs, bucket.second, bucket.first.size());
worker.analyze(equiv, 100 * bucket_count / (buckets.size() + 1));
}
}
}
- lhs.optimize();
- rhs.optimize();
- removed_bits.optimize();
-
if (removed_bits.size())
log("Warning: ignoring initial value on non-register: %s\n", log_signal(removed_bits));
if (!satgen.initial_state.check_all(big_lhs)) {
RTLIL::SigSpec rem = satgen.initial_state.remove(big_lhs);
- rem.optimize();
log_cmd_error("Found -set-init bits that are not part of the initial_state: %s\n", log_signal(rem));
}
projects / yosys.git / commitdiff