i965/blorp: Get rid of brw_blorp_surface_info::width/height

Instead, we manually mutate the surface size as needed.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
index 0f45a6ae39469b80d93b064ff263ee4a2be762e2..78707ca8fd83a1e944a98c9037f806c0086578ed 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -203,8 +203,6 @@ brw_blorp_surface_info_init(struct brw_context *brw,
 
    info->level = level;
    info->layer = layer;
-   info->width = minify(mt->physical_width0, level - mt->first_level);
-   info->height = minify(mt->physical_height0, level - mt->first_level);
 
    if (format == MESA_FORMAT_NONE)
       format = mt->format;
@@ -373,19 +371,6 @@ brw_blorp_emit_surface_state(struct brw_context *brw,
 
    struct isl_surf surf = surface->surf;
 
-   /* Stomp surface dimensions and tiling (if needed) with info from blorp */
-   surf.logical_level0_px.width = surface->width;
-   surf.logical_level0_px.height = surface->height;
-
-   if (brw->gen == 6 && surf.samples > 1) {
-      /* Since gen6 uses INTEL_MSAA_LAYOUT_IMS, width and height are measured
-       * in samples.  But SURFACE_STATE wants them in pixels, so we need to
-       * divide them each by 2.
-       */
-      surf.logical_level0_px.width /= 2;
-      surf.logical_level0_px.height /= 2;
-   }
-
    union isl_color_value clear_color = { .u32 = { 0, 0, 0, 0 } };
 
    const struct isl_surf *aux_surf = NULL;
@@ -619,16 +604,13 @@ gen6_blorp_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
     * prevents the clobbering.
     */
    params.dst.surf.samples = MAX2(mt->num_samples, 1);
-   if (params.depth.surf.samples > 1) {
-      params.depth.width = ALIGN(mt->logical_width0, 8);
-      params.depth.height = ALIGN(mt->logical_height0, 4);
-   } else {
-      params.depth.width = ALIGN(params.depth.width, 8);
-      params.depth.height = ALIGN(params.depth.height, 4);
-   }
+   params.depth.surf.logical_level0_px.width =
+      ALIGN(params.depth.surf.logical_level0_px.width, 8);
+   params.depth.surf.logical_level0_px.height =
+      ALIGN(params.depth.surf.logical_level0_px.height, 4);
 
-   params.x1 = params.depth.width;
-   params.y1 = params.depth.height;
+   params.x1 = params.depth.surf.logical_level0_px.width;
+   params.y1 = params.depth.surf.logical_level0_px.height;
 
    assert(intel_miptree_level_has_hiz(mt, level));
 

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h b/src/mesa/drivers/dri/i965/brw_blorp.h
index 185406e947638430a8c9a3764e3602749b98f8a1..282235d28512fe60052e754f9b97ea291c88f90f 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -94,18 +94,6 @@ struct brw_blorp_surface_info
     */
    uint32_t layer;
 
-   /**
-    * Width of the miplevel to be used.  For surfaces using
-    * INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not pixels.
-    */
-   uint32_t width;
-
-   /**
-    * Height of the miplevel to be used.  For surfaces using
-    * INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not pixels.
-    */
-   uint32_t height;
-
    uint32_t bo_offset;
    uint32_t tile_x_sa, tile_y_sa;
 };

diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index e9d15495ab21785d35a97eda9c6c085b454392d8..4077073404b325013f6ab8c9aa4a362261036100 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -1793,24 +1793,31 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
          params.y0 = ROUND_DOWN_TO(params.y0, 4);
          params.x1 = ALIGN(params.x1 * 2, 4);
          params.y1 = ALIGN(params.y1, 4);
+         params.dst.surf.logical_level0_px.width *= 2;
          break;
       case 4:
          params.x0 = ROUND_DOWN_TO(params.x0 * 2, 4);
          params.y0 = ROUND_DOWN_TO(params.y0 * 2, 4);
          params.x1 = ALIGN(params.x1 * 2, 4);
          params.y1 = ALIGN(params.y1 * 2, 4);
+         params.dst.surf.logical_level0_px.width *= 2;
+         params.dst.surf.logical_level0_px.height *= 2;
          break;
       case 8:
          params.x0 = ROUND_DOWN_TO(params.x0 * 4, 8);
          params.y0 = ROUND_DOWN_TO(params.y0 * 2, 4);
          params.x1 = ALIGN(params.x1 * 4, 8);
          params.y1 = ALIGN(params.y1 * 2, 4);
+         params.dst.surf.logical_level0_px.width *= 4;
+         params.dst.surf.logical_level0_px.height *= 2;
          break;
       case 16:
          params.x0 = ROUND_DOWN_TO(params.x0 * 4, 8);
          params.y0 = ROUND_DOWN_TO(params.y0 * 4, 8);
          params.x1 = ALIGN(params.x1 * 4, 8);
          params.y1 = ALIGN(params.y1 * 4, 8);
+         params.dst.surf.logical_level0_px.width *= 4;
+         params.dst.surf.logical_level0_px.height *= 4;
          break;
       default:
          unreachable("Unrecognized sample count in brw_blorp_blit_params ctor");
@@ -1895,8 +1902,10 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
       params.y0 = ROUND_DOWN_TO(params.y0, y_align) / 2;
       params.x1 = ALIGN(params.x1, x_align) * 2;
       params.y1 = ALIGN(params.y1, y_align) / 2;
-      params.dst.width = ALIGN(params.dst.width, x_align) * 2;
-      params.dst.height = ALIGN(params.dst.height, y_align) / 2;
+      params.dst.surf.logical_level0_px.width =
+         ALIGN(params.dst.surf.logical_level0_px.width, x_align) * 2;
+      params.dst.surf.logical_level0_px.height =
+         ALIGN(params.dst.surf.logical_level0_px.height, y_align) / 2;
       params.dst.tile_x_sa *= 2;
       params.dst.tile_y_sa /= 2;
       wm_prog_key.use_kill = true;
@@ -1920,8 +1929,10 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
        * TODO: what if this makes the texture size too large?
        */
       const unsigned x_align = 8, y_align = params.src.surf.samples != 0 ? 8 : 4;
-      params.src.width = ALIGN(params.src.width, x_align) * 2;
-      params.src.height = ALIGN(params.src.height, y_align) / 2;
+      params.src.surf.logical_level0_px.width =
+         ALIGN(params.src.surf.logical_level0_px.width, x_align) * 2;
+      params.src.surf.logical_level0_px.height =
+         ALIGN(params.src.surf.logical_level0_px.height, y_align) / 2;
       params.src.tile_x_sa *= 2;
       params.src.tile_y_sa /= 2;
    }

diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.c b/src/mesa/drivers/dri/i965/gen6_blorp.c
index 0ee66840c91a0defc7230f0fabc421efae2e3c29..402c2192ad3c3a5119a7749563eb5093d009a64a 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen6_blorp.c
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.c
@@ -730,8 +730,8 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context *brw,
        * larger to allow the fast depth clear to fit the hardware
        * alignment requirements. (8x4)
        */
-      surfwidth = params->depth.width;
-      surfheight = params->depth.height;
+      surfwidth = params->depth.surf.logical_level0_px.width;
+      surfheight = params->depth.surf.logical_level0_px.height;
    } else {
       surfwidth = params->depth.mt->logical_width0;
       surfheight = params->depth.mt->logical_height0;

diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.c b/src/mesa/drivers/dri/i965/gen7_blorp.c
index 7f365bdd9592114dae2aa27646741673fc0e3b3c..ac7cf38189d1585a436a18041a5678300195496e 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_blorp.c
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.c
@@ -521,8 +521,8 @@ gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
        * larger to allow the fast depth clear to fit the hardware
        * alignment requirements. (8x4)
        */
-      surfwidth = params->depth.width;
-      surfheight = params->depth.height;
+      surfwidth = params->depth.surf.logical_level0_px.width;
+      surfheight = params->depth.surf.logical_level0_px.height;
    } else {
       surfwidth = params->depth.mt->logical_width0;
       surfheight = params->depth.mt->logical_height0;