soc/cores/cpu: add reset signal

diff --git a/litex/soc/cores/cpu/lm32/core.py b/litex/soc/cores/cpu/lm32/core.py
index 2ab62c7867791338b37341ccaf24d83867293e31..0d92195c9fc636b07467b0db9cdc92619fcaa15c 100644 (file)
--- a/litex/soc/cores/cpu/lm32/core.py
+++ b/litex/soc/cores/cpu/lm32/core.py
@@ -7,6 +7,7 @@ from litex.soc.interconnect import wishbone
 
 class LM32(Module):
     def __init__(self, platform, eba_reset, variant=None):
+        self.reset = Signal()
         assert variant == None, "No lm32 variants currently supported."
         self.ibus = i = wishbone.Interface()
         self.dbus = d = wishbone.Interface()
@@ -20,7 +21,7 @@ class LM32(Module):
             p_eba_reset=Instance.PreformattedParam("32'h{:08x}".format(eba_reset)),
 
             i_clk_i=ClockSignal(),
-            i_rst_i=ResetSignal(),
+            i_rst_i=ResetSignal() | self.reset,
 
             i_interrupt=self.interrupt,
 

diff --git a/litex/soc/cores/cpu/mor1kx/core.py b/litex/soc/cores/cpu/mor1kx/core.py
index 8ce397dbd8ad1a6def69adbaf2382738a61c9600..3c7b451adaeef092d3c05f0285540cfb75f56298 100644 (file)
--- a/litex/soc/cores/cpu/mor1kx/core.py
+++ b/litex/soc/cores/cpu/mor1kx/core.py
@@ -8,6 +8,7 @@ from litex.soc.interconnect import wishbone
 class MOR1KX(Module):
     def __init__(self, platform, reset_pc, variant=None):
         assert variant in (None, "linux"), "Unsupported variant %s" % variant
+        self.reset = Signal()
         self.ibus = i = wishbone.Interface()
         self.dbus = d = wishbone.Interface()
         self.interrupt = Signal(32)
@@ -69,7 +70,7 @@ class MOR1KX(Module):
             **cpu_args,
 
             i_clk=ClockSignal(),
-            i_rst=ResetSignal(),
+            i_rst=ResetSignal() | self.reset,
 
             i_irq_i=self.interrupt,
 

diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py
index b94a346d9cae7115ff2da003b421e2bc9ebe6308..1fef0edc399d10f729f6f4446b011e545b7c63b1 100644 (file)
--- a/litex/soc/cores/cpu/vexriscv/core.py
+++ b/litex/soc/cores/cpu/vexriscv/core.py
@@ -8,6 +8,7 @@ from litex.soc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage
 class VexRiscv(Module, AutoCSR):
     def __init__(self, platform, cpu_reset_address, variant=None):
         assert variant in (None, "debug"), "Unsupported variant %s" % variant
+        self.reset = Signal()
         self.ibus = i = wishbone.Interface()
         self.dbus = d = wishbone.Interface()
         i_err = Signal()
@@ -113,7 +114,7 @@ class VexRiscv(Module, AutoCSR):
                 **cpu_args,
 
                 i_clk=ClockSignal(),
-                i_reset=cpu_reset,
+                i_reset=cpu_reset | self.reset,
 
                 i_externalResetVector=cpu_reset_address,
                 i_externalInterruptArray=self.interrupt,