Added support for "assign" statements in abc vlparse

diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc
index 5ceaeb48f199080d1be8a34ed4f27b831fdb47e3..94adf6d066e65831c56ae4e8cd70bc11c469464b 100644 (file)
--- a/passes/abc/abc.cc
+++ b/passes/abc/abc.cc
@@ -572,6 +572,14 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
                        }
                }
 
+               for (auto conn : mapped_mod->connections) {
+                       if (!conn.first.is_fully_const())
+                               conn.first = RTLIL::SigSpec(module->wires[remap_name(conn.first.chunks[0].wire->name)]);
+                       if (!conn.second.is_fully_const())
+                               conn.second = RTLIL::SigSpec(module->wires[remap_name(conn.second.chunks[0].wire->name)]);
+                       module->connections.push_back(conn);
+               }
+
                for (auto &it : cell_stats)
                        log("ABC RESULTS:   %15s cells: %8d\n", it.first.c_str(), it.second);
                int in_wires = 0, out_wires = 0;

diff --git a/passes/abc/vlparse.cc b/passes/abc/vlparse.cc
index 5c0cb7e24628338b0f2184462b61a933533aa463..fe10f57b1a523de14c328f4d8e2696fc741961de 100644 (file)
--- a/passes/abc/vlparse.cc
+++ b/passes/abc/vlparse.cc
@@ -53,12 +53,12 @@ static int lex(FILE *f)
                return token(lex_tok);
        
        if (('a' <= ch && ch <= 'z') || ('A' <= ch && ch <= 'Z') ||
-                       ('0' <= ch && ch <= '9') || ch == '_') {
+                       ('0' <= ch && ch <= '9') || ch == '_' || ch == '\'') {
                lex_str = char(ch);
                while (1) {
                        ch = getc(f);
                        if (('a' <= ch && ch <= 'z') || ('A' <= ch && ch <= 'Z') ||
-                                       ('0' <= ch && ch <= '9') || ch == '_') {
+                                       ('0' <= ch && ch <= '9') || ch == '_' || ch == '\'') {
                                lex_str += char(ch);
                                continue;
                        }
@@ -143,6 +143,35 @@ RTLIL::Design *abc_parse_verilog(FILE *f)
                                }
                        }
                }
+               else if (lex_str == "assign")
+               {
+                       std::string lhs, rhs;
+
+                       if (lex(f) != 256)
+                               goto error;
+                       lhs = lex_str;
+
+                       if (lex(f) != '=')
+                               goto error;
+                       if (lex(f) != 256)
+                               goto error;
+                       rhs = lex_str;
+
+                       if (lex(f) != ';')
+                               goto error;
+
+                       if (module->wires.count(RTLIL::escape_id(lhs)) == 0)
+                               goto error;
+
+                       if (rhs == "1'b0")
+                               module->connections.push_back(RTLIL::SigSig(module->wires.at(RTLIL::escape_id(lhs)), RTLIL::SigSpec(0, 1)));
+                       else if (rhs == "1'b1")
+                               module->connections.push_back(RTLIL::SigSig(module->wires.at(RTLIL::escape_id(lhs)), RTLIL::SigSpec(1, 1)));
+                       else if (module->wires.count(RTLIL::escape_id(rhs)) > 0)
+                               module->connections.push_back(RTLIL::SigSig(module->wires.at(RTLIL::escape_id(lhs)), module->wires.at(RTLIL::escape_id(rhs))));
+                       else
+                               goto error;
+               }
                else
                {
                        std::string cell_type = lex_str;