power: Added support for CR, XER, FPSR, MSR, PTCR Registers

Define Condition Register (CR), XER, FPSR, MSR, PTCR Registers
as miscelleneous registers.

In particular, annotate the bits of MSR and PTCR for future use.

Signed-off-by: Phanikiran Harithas <phanikiran.harithas@gmail.com>
Signed-off-by:  Venkatnarayan Kulkarni <venkatnarayankulkarni@gmail.com>
Change-Id: I6f1490b1490e16f9095075f5cd0056894fbf6608

diff --git a/src/arch/power/miscregs.hh b/src/arch/power/miscregs.hh
index c6e5045bca6eda83e4261e80b75ae5647fa6b4e5..0e10e053f0f67eb89dff85f030520dc3f9daddb9 100644 (file)
--- a/src/arch/power/miscregs.hh
+++ b/src/arch/power/miscregs.hh
@@ -35,12 +35,23 @@ namespace PowerISA
 {
 
 enum MiscRegIndex {
-    NUM_MISCREGS = 0
+    MISCREG_CR,
+    MISCREG_XER,
+    MISCREG_FPSR,
+    MISCREG_MSR,
+    MISCREG_PTCR,
+    NUM_MISCREGS
 };
 
 const char * const miscRegName[NUM_MISCREGS] = {
 };
 
+static inline bool
+isValidMiscReg(int index)
+{
+    return (index >= MISCREG_CR && index < NUM_MISCREGS);
+}
+
 BitUnion32(Cr)
     SubBitUnion(cr0, 31, 28)
         Bitfield<31> lt;
@@ -95,6 +106,32 @@ BitUnion32(Fpscr)
     Bitfield<2,1> rn;
 EndBitUnion(Fpscr)
 
+BitUnion64(Msr)
+    Bitfield<63> sf;
+    Bitfield<60> hv;
+    Bitfield<32> tm;
+    Bitfield<34,33> ts;
+    Bitfield<25> vec;
+    Bitfield<23> vsx;
+    Bitfield<15> ee;
+    Bitfield<14> pr;
+    Bitfield<13> fp;
+    Bitfield<12> me;
+    Bitfield<11> fe0;
+    Bitfield<10,9> te;
+    Bitfield<8> fe1;
+    Bitfield<5> ir;
+    Bitfield<4> dr;
+    Bitfield<2> pmm;
+    Bitfield<1> ri;
+    Bitfield<0> le;
+EndBitUnion(Msr)
+
+BitUnion64(Ptcr)
+    Bitfield<59,12> patb;
+    Bitfield<4,0> pats;
+EndBitUnion(Ptcr)
+
 } // namespace PowerISA
 
 #endif // __ARCH_POWER_MISCREGS_HH__

diff --git a/src/arch/power/system.cc b/src/arch/power/system.cc
index 715c3c3e698d56759899f8dd654c102207630303..c1a3bee3e4cda855b8d449df6aaa793a9c44b222 100644 (file)
--- a/src/arch/power/system.cc
+++ b/src/arch/power/system.cc
@@ -68,4 +68,8 @@ PowerSystem::initState()
     System::initState();
     ThreadContext *tc = threadContexts[0];
     tc->pcState(tc->getSystemPtr()->kernelEntry);
+    //Sixty Four, little endian,Hypervisor bits are enabled.
+    // IR and DR bits are disabled.
+    Msr msr = 0x9000000000000001;
+    tc->setIntReg(INTREG_MSR , msr);
 }