RISC-V: Add support for the Zvbc extension

Zvbc is part of the crypto vector extensions.

This extension adds the following instructions:
- vclmul.[vv,vx]
- vclmulh.[vv,vx]

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_multi_subset_supports): Add instruction
	class support for Zvbc.
	(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:

	* testsuite/gas/riscv/zvbc.d: New test.
	* testsuite/gas/riscv/zvbc.s: New test.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_VCLMUL_VV): New.
	(MASK_VCLMUL_VV): New.
	(MATCH_VCLMUL_VX): New.
	(MASK_VCLMUL_VX): New.
	(MATCH_VCLMULH_VV): New.
	(MASK_VCLMULH_VV): New.
	(MATCH_VCLMULH_VX): New.
	(MASK_VCLMULH_VX): New.
	(DECLARE_INSN): New.
	* opcode/riscv.h (enum riscv_insn_class): Add instruction class
	  support for Zvbc.

opcodes/ChangeLog:

	* riscv-opc.c: Add Zvbc instruction.

Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 21a4dc8ae8b838646e56ee82d8f49d5bade1669c..295e0d2c942624857aa505d8d73f8b1ed36a9c0c 100644 (file)
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1263,6 +1263,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zve64f",           ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {"zve64d",           ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {"zvbb",             ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
+  {"zvbc",             ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {"zvl32b",           ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {"zvl64b",           ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {"zvl128b",          ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
@@ -2430,6 +2431,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
              || riscv_subset_supports (rps, "zve32f"));
     case INSN_CLASS_ZVBB:
       return riscv_subset_supports (rps, "zvbb");
+    case INSN_CLASS_ZVBC:
+      return riscv_subset_supports (rps, "zvbc");
     case INSN_CLASS_SVINVAL:
       return riscv_subset_supports (rps, "svinval");
     case INSN_CLASS_H:
@@ -2620,6 +2623,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return _("v' or `zve64d' or `zve64f' or `zve32f");
     case INSN_CLASS_ZVBB:
       return _("zvbb");
+    case INSN_CLASS_ZVBC:
+      return _("zvbc");
     case INSN_CLASS_SVINVAL:
       return "svinval";
     case INSN_CLASS_H:

diff --git a/gas/testsuite/gas/riscv/zvbc.d b/gas/testsuite/gas/riscv/zvbc.d
new file mode 100644 (file)
index 0000000..d9213b2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvbc.d
@@ -0,0 +1,16 @@
+#as: -march=rv64gc_zvbc
+#objdump: -dr
+
+.*:[   ]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[      ]+[0-9a-f]+:[   ]+32862257[     ]+vclmul.vv[    ]+v4,v8,v12
+[      ]+[0-9a-f]+:[   ]+30862257[     ]+vclmul.vv[    ]+v4,v8,v12,v0.t
+[      ]+[0-9a-f]+:[   ]+3285e257[     ]+vclmul.vx[    ]+v4,v8,a1
+[      ]+[0-9a-f]+:[   ]+3085e257[     ]+vclmul.vx[    ]+v4,v8,a1,v0.t
+[      ]+[0-9a-f]+:[   ]+36862257[     ]+vclmulh.vv[   ]+v4,v8,v12
+[      ]+[0-9a-f]+:[   ]+34862257[     ]+vclmulh.vv[   ]+v4,v8,v12,v0.t
+[      ]+[0-9a-f]+:[   ]+3685e257[     ]+vclmulh.vx[   ]+v4,v8,a1
+[      ]+[0-9a-f]+:[   ]+3485e257[     ]+vclmulh.vx[   ]+v4,v8,a1,v0.t

diff --git a/gas/testsuite/gas/riscv/zvbc.s b/gas/testsuite/gas/riscv/zvbc.s
new file mode 100644 (file)
index 0000000..c302d1e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvbc.s
@@ -0,0 +1,8 @@
+       vclmul.vv v4, v8, v12
+       vclmul.vv v4, v8, v12, v0.t
+       vclmul.vx v4, v8, a1
+       vclmul.vx v4, v8, a1, v0.t
+       vclmulh.vv v4, v8, v12
+       vclmulh.vv v4, v8, v12, v0.t
+       vclmulh.vx v4, v8, a1
+       vclmulh.vx v4, v8, a1, v0.t

diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 9003200d2d40e0b8580c89d05924a8f0d72a1fc3..6102feaa5577f4565f67938d31a0d769345020da 100644 (file)
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2154,6 +2154,15 @@
 #define MASK_VWSLL_VV 0xfc00707f
 #define MATCH_VWSLL_VX 0xd4004057
 #define MASK_VWSLL_VX 0xfc00707f
+/* Zvbc instructions. */
+#define MATCH_VCLMUL_VV 0x30002057
+#define MASK_VCLMUL_VV 0xfc00707f
+#define MATCH_VCLMUL_VX 0x30006057
+#define MASK_VCLMUL_VX 0xfc00707f
+#define MATCH_VCLMULH_VV 0x34002057
+#define MASK_VCLMULH_VV 0xfc00707f
+#define MATCH_VCLMULH_VX 0x34006057
+#define MASK_VCLMULH_VX 0xfc00707f
 /* Svinval instruction.  */
 #define MATCH_SINVAL_VMA 0x16000073
 #define MASK_SINVAL_VMA 0xfe007fff
@@ -3280,6 +3289,11 @@ DECLARE_INSN(vror_vx, MATCH_VROR_VX, MASK_VROR_VX)
 DECLARE_INSN(vwsll_vi, MATCH_VWSLL_VI, MASK_VWSLL_VI)
 DECLARE_INSN(vwsll_vv, MATCH_VWSLL_VV, MASK_VWSLL_VV)
 DECLARE_INSN(vwsll_vx, MATCH_VWSLL_VX, MASK_VWSLL_VX)
+/* Zvbc instructions.  */
+DECLARE_INSN(vclmul_vv, MATCH_VCLMUL_VV, MASK_VCLMUL_VV)
+DECLARE_INSN(vclmul_vx, MATCH_VCLMUL_VX, MASK_VCLMUL_VX)
+DECLARE_INSN(vclmulh_vv, MATCH_VCLMULH_VV, MASK_VCLMULH_VV)
+DECLARE_INSN(vclmulh_vx, MATCH_VCLMULH_VX, MASK_VCLMULH_VX)
 /* Vendor-specific (T-Head) XTheadBa instructions.  */
 DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
 /* Vendor-specific (T-Head) XTheadBb instructions.  */

diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 487856478f30e02c93c4a664110f9fe0add77888..783b1c01e52cfd17f6caec708baa14f46dd53586 100644 (file)
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -415,6 +415,7 @@ enum riscv_insn_class
   INSN_CLASS_V,
   INSN_CLASS_ZVEF,
   INSN_CLASS_ZVBB,
+  INSN_CLASS_ZVBC,
   INSN_CLASS_SVINVAL,
   INSN_CLASS_ZICBOM,
   INSN_CLASS_ZICBOP,

diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 6e8313bac16d0bbb38c209ecc62d145d469cd90a..19a72903510c25ede928d05f6cb73d0025c4e0fb 100644 (file)
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1902,6 +1902,12 @@ const struct riscv_opcode riscv_opcodes[] =
 {"vwsll.vx",    0, INSN_CLASS_ZVBB, "Vd,Vt,sVm", MATCH_VWSLL_VX, MASK_VWSLL_VX, match_opcode, 0},
 {"vwsll.vi",    0, INSN_CLASS_ZVBB, "Vd,Vt,VjVm", MATCH_VWSLL_VI, MASK_VWSLL_VI, match_opcode, 0},
 
+/* Zvbc instructions.  */
+{"vclmul.vv",   0, INSN_CLASS_ZVBC, "Vd,Vt,VsVm", MATCH_VCLMUL_VV, MASK_VCLMUL_VV, match_opcode, 0},
+{"vclmul.vx",   0, INSN_CLASS_ZVBC, "Vd,Vt,sVm", MATCH_VCLMUL_VX, MASK_VCLMUL_VX, match_opcode, 0},
+{"vclmulh.vv",   0, INSN_CLASS_ZVBC, "Vd,Vt,VsVm", MATCH_VCLMULH_VV, MASK_VCLMULH_VV, match_opcode, 0},
+{"vclmulh.vx",   0, INSN_CLASS_ZVBC, "Vd,Vt,sVm", MATCH_VCLMULH_VX, MASK_VCLMULH_VX, match_opcode, 0},
+
 /* Supervisor instructions.  */
 {"csrr",       0, INSN_CLASS_ZICSR, "d,E",   MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },
 {"csrw",       0, INSN_CLASS_ZICSR, "E,s",   MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS },