sim_objects = m5.SimObject.allClasses
all_enums = m5.params.allEnums
+if m5.SimObject.noCxxHeader:
+ print >> sys.stderr, \
+ "warning: At least one SimObject lacks a header specification. " \
+ "This can cause unexpected results in the generated SWIG " \
+ "wrappers."
+
# Find param types that need to be explicitly wrapped with swig.
# These will be recognized because the ParamDesc will have a
# swig_decl() method. Most param types are based on types that don't
class AlphaInterrupts(SimObject):
type = 'AlphaInterrupts'
cxx_class = 'AlphaISA::Interrupts'
+ cxx_header = "arch/alpha/interrupts.hh"
class AlphaSystem(System):
type = 'AlphaSystem'
+ cxx_header = "arch/alpha/system.hh"
console = Param.String("file that contains the console code")
pal = Param.String("file that contains palcode")
system_type = Param.UInt64("Type of system we are emulating")
class LinuxAlphaSystem(AlphaSystem):
type = 'LinuxAlphaSystem'
+ cxx_header = "arch/alpha/linux/system.hh"
system_type = 34
system_rev = 1 << 10
class FreebsdAlphaSystem(AlphaSystem):
type = 'FreebsdAlphaSystem'
+ cxx_header = "arch/alpha/freebsd/system.hh"
system_type = 34
system_rev = 1 << 10
class Tru64AlphaSystem(AlphaSystem):
type = 'Tru64AlphaSystem'
+ cxx_header = "arch/alpha/tru64/system.hh"
system_type = 12
system_rev = 2<<1
class AlphaTLB(BaseTLB):
type = 'AlphaTLB'
cxx_class = 'AlphaISA::TLB'
+ cxx_header = "arch/alpha/tlb.hh"
size = Param.Int("TLB size")
class AlphaDTB(AlphaTLB):
class ArmInterrupts(SimObject):
type = 'ArmInterrupts'
cxx_class = 'ArmISA::Interrupts'
+ cxx_header = "arch/arm/interrupts.hh"
class ArmNativeTrace(NativeTrace):
type = 'ArmNativeTrace'
cxx_class = 'Trace::ArmNativeTrace'
+ cxx_header = "arch/arm/nativetrace.hh"
stop_on_pc_error = Param.Bool(True,
"Stop M5 if it and statetrace's pcs are different")
class ArmSystem(System):
type = 'ArmSystem'
+ cxx_header = "arch/arm/system.hh"
load_addr_mask = 0xffffffff
# 0x35 Implementor is '5' from "M5"
# 0x0 Variant
class LinuxArmSystem(ArmSystem):
type = 'LinuxArmSystem'
+ cxx_header = "arch/arm/linux/system.hh"
load_addr_mask = 0x0fffffff
machine_type = Param.ArmMachineType('RealView_PBX',
"Machine id from http://www.arm.linux.org.uk/developer/machines/")
class ArmTableWalker(MemObject):
type = 'ArmTableWalker'
cxx_class = 'ArmISA::TableWalker'
+ cxx_header = "arch/arm/table_walker.hh"
port = MasterPort("Port for TableWalker to do walk the translation with")
sys = Param.System(Parent.any, "system object parameter")
num_squash_per_cycle = Param.Unsigned(2,
class ArmTLB(SimObject):
type = 'ArmTLB'
cxx_class = 'ArmISA::TLB'
+ cxx_header = "arch/arm/tlb.hh"
size = Param.Int(64, "TLB size")
walker = Param.ArmTableWalker(ArmTableWalker(), "HW Table walker")
class MipsInterrupts(SimObject):
type = 'MipsInterrupts'
cxx_class = 'MipsISA::Interrupts'
+ cxx_header = 'arch/mips/interrupts.hh'
class MipsSystem(System):
type = 'MipsSystem'
+ cxx_header = 'arch/mips/system.hh'
console = Param.String("file that contains the console code")
bare_iron = Param.Bool(False, "Using Bare Iron Mode?")
hex_file_name = Param.String("test.hex","hex file that contains [address,data] pairs")
class LinuxMipsSystem(MipsSystem):
type = 'LinuxMipsSystem'
+ cxx_header = 'arch/mips/linux/system.hh'
system_type = 34
system_rev = 1 << 10
class BareIronMipsSystem(MipsSystem):
type = 'BareIronMipsSystem'
+ cxx_header = 'arch/mips/bare_iron/system.hh'
bare_iron = True
system_type = 34
system_rev = 1 << 10
class MipsTLB(BaseTLB):
type = 'MipsTLB'
cxx_class = 'MipsISA::TLB'
+ cxx_header = 'arch/mips/tlb.hh'
size = Param.Int(64, "TLB size")
class PowerInterrupts(SimObject):
type = 'PowerInterrupts'
cxx_class = 'PowerISA::Interrupts'
+ cxx_header = 'arch/power/interrupts.hh'
class PowerTLB(SimObject):
type = 'PowerTLB'
cxx_class = 'PowerISA::TLB'
+ cxx_header = 'arch/power/tlb.hh'
size = Param.Int(64, "TLB size")
class SparcInterrupts(SimObject):
type = 'SparcInterrupts'
cxx_class = 'SparcISA::Interrupts'
+ cxx_header = 'arch/sparc/interrupts.hh'
class SparcNativeTrace(NativeTrace):
type = 'SparcNativeTrace'
cxx_class = 'Trace::SparcNativeTrace'
+ cxx_header = 'arch/sparc/nativetrace.hh'
class SparcSystem(System):
type = 'SparcSystem'
+ cxx_header = 'arch/sparc/system.hh'
_rom_base = 0xfff0000000
_nvram_base = 0x1f11000000
_hypervisor_desc_base = 0x1f12080000
class SparcTLB(BaseTLB):
type = 'SparcTLB'
cxx_class = 'SparcISA::TLB'
+ cxx_header = 'arch/sparc/tlb.hh'
size = Param.Int(64, "TLB size")
class X86LocalApic(BasicPioDevice):
type = 'X86LocalApic'
cxx_class = 'X86ISA::Interrupts'
+ cxx_header = 'arch/x86/interrupts.hh'
int_master = MasterPort("Port for sending interrupt messages")
int_slave = SlavePort("Port for receiving interrupt messages")
int_latency = Param.Latency('1ns', \
class X86NativeTrace(NativeTrace):
type = 'X86NativeTrace'
cxx_class = 'Trace::X86NativeTrace'
+ cxx_header = 'arch/x86/nativetrace.hh'
class X86System(System):
type = 'X86System'
+ cxx_header = 'arch/x86/system.hh'
smbios_table = Param.X86SMBiosSMBiosTable(
X86SMBiosSMBiosTable(), 'table of smbios/dmi information')
intel_mp_pointer = Param.X86IntelMPFloatingPointer(
class LinuxX86System(X86System):
type = 'LinuxX86System'
+ cxx_header = 'arch/x86/linux/system.hh'
e820_table = Param.X86E820Table(
X86E820Table(), 'E820 map of physical memory')
class X86PagetableWalker(MemObject):
type = 'X86PagetableWalker'
cxx_class = 'X86ISA::Walker'
+ cxx_header = 'arch/x86/pagetable_walker.hh'
port = MasterPort("Port for the hardware table walker")
system = Param.System(Parent.any, "system object")
class X86TLB(BaseTLB):
type = 'X86TLB'
cxx_class = 'X86ISA::TLB'
+ cxx_header = 'arch/x86/tlb.hh'
size = Param.Int(64, "TLB size")
walker = Param.X86PagetableWalker(\
X86PagetableWalker(), "page table walker")
class X86ACPISysDescTable(SimObject):
type = 'X86ACPISysDescTable'
cxx_class = 'X86ISA::ACPI::SysDescTable'
+ cxx_header = 'arch/x86/bios/acpi.hh'
abstract = True
oem_id = Param.String('', 'string identifying the oem')
class X86ACPIRSDT(X86ACPISysDescTable):
type = 'X86ACPIRSDT'
cxx_class = 'X86ISA::ACPI::RSDT'
+ cxx_header = 'arch/x86/bios/acpi.hh'
entries = VectorParam.X86ACPISysDescTable([], 'system description tables')
class X86ACPIXSDT(X86ACPISysDescTable):
type = 'X86ACPIXSDT'
cxx_class = 'X86ISA::ACPI::XSDT'
+ cxx_header = 'arch/x86/bios/acpi.hh'
entries = VectorParam.X86ACPISysDescTable([], 'system description tables')
class X86ACPIRSDP(SimObject):
type = 'X86ACPIRSDP'
cxx_class = 'X86ISA::ACPI::RSDP'
+ cxx_header = 'arch/x86/bios/acpi.hh'
oem_id = Param.String('', 'string identifying the oem')
# Because 0 encodes ACPI 1.0, 2 encodes ACPI 3.0, the version implemented
class X86E820Entry(SimObject):
type = 'X86E820Entry'
cxx_class = 'X86ISA::E820Entry'
+ cxx_header = 'arch/x86/bios/e820.hh'
addr = Param.Addr(0, 'address of the beginning of the region')
size = Param.MemorySize('0B', 'size of the region')
class X86E820Table(SimObject):
type = 'X86E820Table'
cxx_class = 'X86ISA::E820Table'
+ cxx_header = 'arch/x86/bios/e820.hh'
entries = VectorParam.X86E820Entry('entries for the e820 table')
class X86IntelMPFloatingPointer(SimObject):
type = 'X86IntelMPFloatingPointer'
cxx_class = 'X86ISA::IntelMP::FloatingPointer'
+ cxx_header = 'arch/x86/bios/intelmp.hh'
# The minor revision of the spec to support. The major version is assumed
# to be 1 in accordance with the spec.
class X86IntelMPConfigTable(SimObject):
type = 'X86IntelMPConfigTable'
cxx_class = 'X86ISA::IntelMP::ConfigTable'
+ cxx_header = 'arch/x86/bios/intelmp.hh'
spec_rev = Param.UInt8(4, 'minor revision of the MP spec supported')
oem_id = Param.String("", 'system manufacturer')
class X86IntelMPBaseConfigEntry(SimObject):
type = 'X86IntelMPBaseConfigEntry'
cxx_class = 'X86ISA::IntelMP::BaseConfigEntry'
+ cxx_header = 'arch/x86/bios/intelmp.hh'
abstract = True
class X86IntelMPExtConfigEntry(SimObject):
type = 'X86IntelMPExtConfigEntry'
cxx_class = 'X86ISA::IntelMP::ExtConfigEntry'
+ cxx_header = 'arch/x86/bios/intelmp.hh'
abstract = True
class X86IntelMPProcessor(X86IntelMPBaseConfigEntry):
type = 'X86IntelMPProcessor'
cxx_class = 'X86ISA::IntelMP::Processor'
+ cxx_header = 'arch/x86/bios/intelmp.hh'
local_apic_id = Param.UInt8(0, 'local APIC id')
local_apic_version = Param.UInt8(0,
class X86IntelMPBus(X86IntelMPBaseConfigEntry):
type = 'X86IntelMPBus'
cxx_class = 'X86ISA::IntelMP::Bus'
+ cxx_header = 'arch/x86/bios/intelmp.hh'
bus_id = Param.UInt8(0, 'bus id assigned by the bios')
bus_type = Param.String("", 'string that identify the bus type')
class X86IntelMPIOAPIC(X86IntelMPBaseConfigEntry):
type = 'X86IntelMPIOAPIC'
cxx_class = 'X86ISA::IntelMP::IOAPIC'
+ cxx_header = 'arch/x86/bios/intelmp.hh'
id = Param.UInt8(0, 'id of this APIC')
version = Param.UInt8(0, 'bits 0-7 of the version register')
class X86IntelMPIOIntAssignment(X86IntelMPBaseConfigEntry):
type = 'X86IntelMPIOIntAssignment'
cxx_class = 'X86ISA::IntelMP::IOIntAssignment'
+ cxx_header = 'arch/x86/bios/intelmp.hh'
interrupt_type = Param.X86IntelMPInterruptType('INT', 'type of interrupt')
class X86IntelMPLocalIntAssignment(X86IntelMPBaseConfigEntry):
type = 'X86IntelMPLocalIntAssignment'
cxx_class = 'X86ISA::IntelMP::LocalIntAssignment'
+ cxx_header = 'arch/x86/bios/intelmp.hh'
interrupt_type = Param.X86IntelMPInterruptType('INT', 'type of interrupt')
class X86IntelMPAddrSpaceMapping(X86IntelMPExtConfigEntry):
type = 'X86IntelMPAddrSpaceMapping'
cxx_class = 'X86ISA::IntelMP::AddrSpaceMapping'
+ cxx_header = 'arch/x86/bios/intelmp.hh'
bus_id = Param.UInt8(0, 'id of the bus the address space is mapped to')
address_type = Param.X86IntelMPAddressType('IOAddress',
class X86IntelMPBusHierarchy(X86IntelMPExtConfigEntry):
type = 'X86IntelMPBusHierarchy'
cxx_class = 'X86ISA::IntelMP::BusHierarchy'
+ cxx_header = 'arch/x86/bios/intelmp.hh'
bus_id = Param.UInt8(0, 'id of the bus being described')
subtractive_decode = Param.Bool(False,
class X86IntelMPCompatAddrSpaceMod(X86IntelMPExtConfigEntry):
type = 'X86IntelMPCompatAddrSpaceMod'
cxx_class = 'X86ISA::IntelMP::CompatAddrSpaceMod'
+ cxx_header = 'arch/x86/bios/intelmp.hh'
bus_id = Param.UInt8(0, 'id of the bus being described')
add = Param.Bool(False,
class X86SMBiosSMBiosStructure(SimObject):
type = 'X86SMBiosSMBiosStructure'
cxx_class = 'X86ISA::SMBios::SMBiosStructure'
+ cxx_header = 'arch/x86/bios/smbios.hh'
abstract = True
class Characteristic(Enum):
class X86SMBiosBiosInformation(X86SMBiosSMBiosStructure):
type = 'X86SMBiosBiosInformation'
cxx_class = 'X86ISA::SMBios::BiosInformation'
+ cxx_header = 'arch/x86/bios/smbios.hh'
vendor = Param.String("", "vendor name string")
version = Param.String("", "version string")
class X86SMBiosSMBiosTable(SimObject):
type = 'X86SMBiosSMBiosTable'
cxx_class = 'X86ISA::SMBios::SMBiosTable'
+ cxx_header = 'arch/x86/bios/smbios.hh'
major_version = Param.UInt8(2, "major version number")
minor_version = Param.UInt8(5, "minor version number")
class CPA(SimObject):
type = 'CPA'
+ cxx_header = "base/cp_annotate.hh"
enabled = Param.Bool(False, "Is Annotation enabled?")
user_apps = VectorParam.String([], "List of apps to get symbols for")
class VncInput(SimObject):
type = 'VncInput'
+ cxx_header = "base/vnc/vncinput.hh"
frame_capture = Param.Bool(False, "capture changed frames to files")
class VncServer(VncInput):
type = 'VncServer'
+ cxx_header = "base/vnc/vncserver.hh"
port = Param.TcpPort(5900, "listen port")
number = Param.Int(0, "vnc client number")
class BaseCPU(MemObject):
type = 'BaseCPU'
abstract = True
-
- @classmethod
- def export_method_cxx_predecls(cls, code):
- code('#include "cpu/base.hh"')
-
+ cxx_header = "cpu/base.hh"
@classmethod
def export_methods(cls, code):
class CheckerCPU(BaseCPU):
type = 'CheckerCPU'
abstract = True
+ cxx_header = "cpu/checker/cpu.hh"
exitOnError = Param.Bool(False, "Exit on an error")
updateOnError = Param.Bool(False,
"Update the checker with the main CPU's state on an error")
class ExeTracer(InstTracer):
type = 'ExeTracer'
cxx_class = 'Trace::ExeTracer'
+ cxx_header = "cpu/exetrace.hh"
class OpDesc(SimObject):
type = 'OpDesc'
+ cxx_header = "cpu/func_unit.hh"
issueLat = Param.Cycles(1, "cycles until another can be issued")
opClass = Param.OpClass("type of operation")
opLat = Param.Cycles(1, "cycles until result is available")
class FUDesc(SimObject):
type = 'FUDesc'
+ cxx_header = "cpu/func_unit.hh"
count = Param.Int("number of these FU's available")
opList = VectorParam.OpDesc("operation classes for this FU type")
class IntelTrace(InstTracer):
type = 'IntelTrace'
cxx_class = 'Trace::IntelTrace'
+ cxx_header = "cpu/inteltrace.hh"
from m5.proxy import *
class IntrControl(SimObject):
type = 'IntrControl'
+ cxx_header = "cpu/intr_control.hh"
sys = Param.System(Parent.any, "the system we are part of")
class LegionTrace(InstTracer):
type = 'LegionTrace'
cxx_class = 'Trace::LegionTrace'
+ cxx_header = "cpu/legiontrace.hh"
abstract = True
type = 'NativeTrace'
cxx_class = 'Trace::NativeTrace'
+ cxx_header = "cpu/nativetrace.hh"
class InOrderCPU(BaseCPU):
type = 'InOrderCPU'
+ cxx_header = "cpu/inorder/cpu.hh"
activity = Param.Unsigned(0, "Initial count")
threadModel = Param.ThreadModel('SMT', "Multithreading model (SE-MODE only)")
class InOrderTrace(InstTracer):
type = 'InOrderTrace'
cxx_class = 'Trace::InOrderTrace'
+ cxx_header = "cpu/inorder/inorder_trace.hh"
#include "base/trace.hh"
#include "base/types.hh"
#include "cpu/static_inst.hh"
+#include "cpu/thread_context.hh"
#include "debug/ExecEnable.hh"
#include "debug/ExecSpeculative.hh"
#include "params/IntelTrace.hh"
#include "sim/insttracer.hh"
-class ThreadContext;
-
namespace Trace {
class IntelTraceRecord : public InstRecord
class FUPool(SimObject):
type = 'FUPool'
+ cxx_header = "cpu/o3/fu_pool.hh"
FUList = VectorParam.FUDesc("list of FU's for this pool")
class DefaultFUPool(FUPool):
class AtomicSimpleCPU(BaseSimpleCPU):
type = 'AtomicSimpleCPU'
+ cxx_header = "cpu/simple/atomic.hh"
width = Param.Int(1, "CPU width")
simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles")
simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles")
class BaseSimpleCPU(BaseCPU):
type = 'BaseSimpleCPU'
abstract = True
+ cxx_header = "cpu/simple/base.hh"
def addCheckerCpu(self):
if buildEnv['TARGET_ISA'] in ['arm']:
class TimingSimpleCPU(BaseSimpleCPU):
type = 'TimingSimpleCPU'
+ cxx_header = "cpu/simple/timing.hh"
#include "config/the_isa.hh"
#include "cpu/op_class.hh"
#include "cpu/static_inst_fwd.hh"
+#include "cpu/thread_context.hh"
#include "sim/fault_fwd.hh"
// forward declarations
struct AlphaSimpleImpl;
struct OzoneImpl;
struct SimpleImpl;
-class ThreadContext;
class DynInst;
class Packet;
class DirectedGenerator(SimObject):
type = 'DirectedGenerator'
abstract = True
+ cxx_header = "cpu/testers/directedtest/DirectedGenerator.hh"
num_cpus = Param.Int("num of cpus")
system = Param.System(Parent.any, "System we belong to")
class SeriesRequestGenerator(DirectedGenerator):
type = 'SeriesRequestGenerator'
+ cxx_header = "cpu/testers/directedtest/SeriesRequestGenerator.hh"
addr_increment_size = Param.Int(64, "address increment size")
issue_writes = Param.Bool(True, "issue writes if true, otherwise reads")
class InvalidateGenerator(DirectedGenerator):
type = 'InvalidateGenerator'
+ cxx_header = "cpu/testers/directedtest/InvalidateGenerator.hh"
addr_increment_size = Param.Int(64, "address increment size")
class RubyDirectedTester(MemObject):
type = 'RubyDirectedTester'
+ cxx_header = "cpu/testers/directedtest/RubyDirectedTester.hh"
cpuPort = VectorMasterPort("the cpu ports")
requests_to_complete = Param.Int("checks to complete")
generator = Param.DirectedGenerator("the request generator")
class MemTest(MemObject):
type = 'MemTest'
+ cxx_header = "cpu/testers/memtest/memtest.hh"
max_loads = Param.Counter(0, "number of loads to execute")
atomic = Param.Bool(False, "Execute tester in atomic mode? (or timing)\n")
memory_size = Param.Int(65536, "memory size")
class NetworkTest(MemObject):
type = 'NetworkTest'
+ cxx_header = "cpu/testers/networktest/networktest.hh"
block_offset = Param.Int(6, "block offset in bits")
num_memories = Param.Int(1, "Num Memories")
memory_size = Param.Int(65536, "memory size")
class RubyTester(MemObject):
type = 'RubyTester'
+ cxx_header = "cpu/testers/rubytest/RubyTester.hh"
num_cpus = Param.Int("number of cpus / RubyPorts")
cpuDataPort = VectorMasterPort("the cpu data cache ports")
cpuInstPort = VectorMasterPort("the cpu inst cache ports")
# probabilities, effectively making it a Markov Chain.
class TrafficGen(MemObject):
type = 'TrafficGen'
+ cxx_header = "cpu/testers/traffic_gen/traffic_gen.hh"
# Port used for sending requests and receiving responses
port = MasterPort("Master port")
class BadDevice(BasicPioDevice):
type = 'BadDevice'
+ cxx_header = "dev/baddev.hh"
devicename = Param.String("Name of device to error on")
class CopyEngine(PciDevice):
type = 'CopyEngine'
+ cxx_header = "dev/copy_engine.hh"
dma = VectorMasterPort("Copy engine DMA port")
VendorID = 0x8086
DeviceID = 0x1a38
class PioDevice(MemObject):
type = 'PioDevice'
+ cxx_header = "dev/io_device.hh"
abstract = True
pio = SlavePort("Programmed I/O port")
system = Param.System(Parent.any, "System this device is part of")
class BasicPioDevice(PioDevice):
type = 'BasicPioDevice'
+ cxx_header = "dev/io_device.hh"
abstract = True
pio_addr = Param.Addr("Device Address")
pio_latency = Param.Latency('100ns', "Programmed IO latency")
class DmaDevice(PioDevice):
type = 'DmaDevice'
+ cxx_header = "dev/io_device.hh"
abstract = True
dma = MasterPort("DMA port")
class IsaFake(BasicPioDevice):
type = 'IsaFake'
+ cxx_header = "dev/io_device.hh"
pio_size = Param.Addr(0x8, "Size of address range")
ret_data8 = Param.UInt8(0xFF, "Default data to return")
ret_data16 = Param.UInt16(0xFFFF, "Default data to return")
class DiskImage(SimObject):
type = 'DiskImage'
abstract = True
+ cxx_header = "dev/disk_image.hh"
image_file = Param.String("disk image file")
read_only = Param.Bool(False, "read only image")
class RawDiskImage(DiskImage):
type = 'RawDiskImage'
+ cxx_header = "dev/disk_image.hh"
class CowDiskImage(DiskImage):
type = 'CowDiskImage'
+ cxx_header = "dev/disk_image.hh"
child = Param.DiskImage(RawDiskImage(read_only=True),
"child image")
table_size = Param.Int(65536, "initial table size")
class EtherObject(SimObject):
type = 'EtherObject'
abstract = True
+ cxx_header = "dev/etherobject.hh"
class EtherLink(EtherObject):
type = 'EtherLink'
+ cxx_header = "dev/etherlink.hh"
int0 = SlavePort("interface 0")
int1 = SlavePort("interface 1")
delay = Param.Latency('0us', "packet transmit delay")
class EtherBus(EtherObject):
type = 'EtherBus'
+ cxx_header = "dev/etherbus.hh"
loopback = Param.Bool(True, "send packet back to the sending interface")
dump = Param.EtherDump(NULL, "dump object")
speed = Param.NetworkBandwidth('100Mbps', "bus speed in bits per second")
class EtherTap(EtherObject):
type = 'EtherTap'
+ cxx_header = "dev/ethertap.hh"
bufsz = Param.Int(10000, "tap buffer size")
dump = Param.EtherDump(NULL, "dump object")
port = Param.UInt16(3500, "tap port")
class EtherDump(SimObject):
type = 'EtherDump'
+ cxx_header = "dev/etherdump.hh"
file = Param.String("dump file")
maxlen = Param.Int(96, "max portion of packet data to dump")
class EtherDevice(PciDevice):
type = 'EtherDevice'
abstract = True
+ cxx_header = "dev/etherdevice.hh"
interface = MasterPort("Ethernet Interface")
class IGbE(EtherDevice):
# Base class for two IGbE adapters listed above
type = 'IGbE'
+ cxx_header = "dev/i8254xGBe.hh"
hardware_address = Param.EthernetAddr(NextEthernetAddr,
"Ethernet Hardware Address")
use_flow_control = Param.Bool(False,
class NSGigE(EtherDevBase):
type = 'NSGigE'
+ cxx_header = "dev/ns_gige.hh"
dma_data_free = Param.Bool(False, "DMA of Data is free")
dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
class Sinic(EtherDevBase):
type = 'Sinic'
cxx_class = 'Sinic::Device'
+ cxx_header = "dev/sinic.hh"
rx_max_copy = Param.MemorySize('1514B', "rx max copy")
tx_max_copy = Param.MemorySize('16kB', "tx max copy")
class IdeDisk(SimObject):
type = 'IdeDisk'
+ cxx_header = "dev/ide_disk.hh"
delay = Param.Latency('1us', "Fixed disk delay in microseconds")
driveID = Param.IdeID('master', "Drive ID")
image = Param.DiskImage("Disk image")
class IdeController(PciDevice):
type = 'IdeController'
+ cxx_header = "dev/ide_ctrl.hh"
disks = VectorParam.IdeDisk("IDE disks attached to this controller")
VendorID = 0x8086
class PciConfigAll(PioDevice):
type = 'PciConfigAll'
+ cxx_header = "dev/pciconfigall.hh"
platform = Param.Platform(Parent.any, "Platform this device is part of.")
pio_latency = Param.Latency('30ns', "Programmed IO latency")
bus = Param.UInt8(0x00, "PCI bus to act as config space for")
class PciDevice(DmaDevice):
type = 'PciDevice'
cxx_class = 'PciDev'
+ cxx_header = "dev/pcidev.hh"
abstract = True
platform = Param.Platform(Parent.any, "Platform this device is part of.")
config = SlavePort("PCI configuration space port")
class Platform(SimObject):
type = 'Platform'
abstract = True
+ cxx_header = "dev/platform.hh"
intrctrl = Param.IntrControl(Parent.any, "interrupt controller")
from m5.proxy import *
class SimpleDisk(SimObject):
type = 'SimpleDisk'
+ cxx_header = "dev/simple_disk.hh"
disk = Param.DiskImage("Disk Image")
system = Param.System(Parent.any, "System Pointer")
class Terminal(SimObject):
type = 'Terminal'
+ cxx_header = "dev/terminal.hh"
intr_control = Param.IntrControl(Parent.any, "interrupt controller")
port = Param.TcpPort(3456, "listen port")
number = Param.Int(0, "terminal number")
class Uart(BasicPioDevice):
type = 'Uart'
abstract = True
+ cxx_header = "dev/uart.hh"
platform = Param.Platform(Parent.any, "Platform this device is part of.")
terminal = Param.Terminal(Parent.any, "The terminal")
class Uart8250(Uart):
type = 'Uart8250'
+ cxx_header = "dev/uart8250.hh"
class AlphaBackdoor(BasicPioDevice):
type = 'AlphaBackdoor'
+ cxx_header = "dev/alpha/backdoor.hh"
cpu = Param.BaseCPU(Parent.cpu[0], "Processor")
disk = Param.SimpleDisk("Simple Disk")
terminal = Param.Terminal(Parent.any, "The console terminal")
class TsunamiCChip(BasicPioDevice):
type = 'TsunamiCChip'
+ cxx_header = "dev/alpha/tsunami_cchip.hh"
tsunami = Param.Tsunami(Parent.any, "Tsunami")
class TsunamiIO(BasicPioDevice):
type = 'TsunamiIO'
+ cxx_header = "dev/alpha/tsunami_io.hh"
time = Param.Time('01/01/2009',
"System time to use ('Now' for actual time)")
year_is_bcd = Param.Bool(False,
class TsunamiPChip(BasicPioDevice):
type = 'TsunamiPChip'
+ cxx_header = "dev/alpha/tsunami_pchip.hh"
tsunami = Param.Tsunami(Parent.any, "Tsunami")
class Tsunami(Platform):
type = 'Tsunami'
+ cxx_header = "dev/alpha/tsunami.hh"
system = Param.System(Parent.any, "system")
cchip = TsunamiCChip(pio_addr=0x801a0000000)
#define __DEV_TSUNAMI_IO_HH__
#include "dev/alpha/tsunami.hh"
+#include "dev/alpha/tsunami_cchip.hh"
#include "dev/intel_8254_timer.hh"
#include "dev/io_device.hh"
#include "dev/mc146818.hh"
class AmbaDevice(BasicPioDevice):
type = 'AmbaDevice'
abstract = True
+ cxx_header = "dev/arm/amba_device.hh"
amba_id = Param.UInt32("ID of AMBA device for kernel detection")
class AmbaIntDevice(AmbaDevice):
type = 'AmbaIntDevice'
abstract = True
+ cxx_header = "dev/arm/amba_device.hh"
gic = Param.Gic(Parent.any, "Gic to use for interrupting")
int_num = Param.UInt32("Interrupt number that connects to GIC")
int_delay = Param.Latency("100ns",
class AmbaDmaDevice(DmaDevice):
type = 'AmbaDmaDevice'
abstract = True
+ cxx_header = "dev/arm/amba_device.hh"
pio_addr = Param.Addr("Address for AMBA slave interface")
pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device")
gic = Param.Gic(Parent.any, "Gic to use for interrupting")
class A9SCU(BasicPioDevice):
type = 'A9SCU'
+ cxx_header = "dev/arm/a9scu.hh"
class RealViewCtrl(BasicPioDevice):
type = 'RealViewCtrl'
+ cxx_header = "dev/arm/rv_ctrl.hh"
proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID")
proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1")
idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID")
class Gic(PioDevice):
type = 'Gic'
+ cxx_header = "dev/arm/gic.hh"
platform = Param.Platform(Parent.any, "Platform this device is part of.")
dist_addr = Param.Addr(0x1f001000, "Address for distributor")
cpu_addr = Param.Addr(0x1f000100, "Address for cpu")
class AmbaFake(AmbaDevice):
type = 'AmbaFake'
+ cxx_header = "dev/arm/amba_fake.hh"
ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)")
amba_id = 0;
class Pl011(Uart):
type = 'Pl011'
+ cxx_header = "dev/arm/pl011.hh"
gic = Param.Gic(Parent.any, "Gic to use for interrupting")
int_num = Param.UInt32("Interrupt number that connects to GIC")
end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART")
class Sp804(AmbaDevice):
type = 'Sp804'
+ cxx_header = "dev/arm/timer_sp804.hh"
gic = Param.Gic(Parent.any, "Gic to use for interrupting")
int_num0 = Param.UInt32("Interrupt number that connects to GIC")
clock0 = Param.Clock('1MHz', "Clock speed of the input")
class CpuLocalTimer(BasicPioDevice):
type = 'CpuLocalTimer'
+ cxx_header = "dev/arm/timer_cpulocal.hh"
gic = Param.Gic(Parent.any, "Gic to use for interrupting")
int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC")
int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC")
class PL031(AmbaIntDevice):
type = 'PL031'
+ cxx_header = "dev/arm/rtc_pl031.hh"
time = Param.Time('01/01/2009', "System time to use ('Now' for actual time)")
amba_id = 0x00341031
class Pl050(AmbaIntDevice):
type = 'Pl050'
+ cxx_header = "dev/arm/kmi.hh"
vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display")
is_mouse = Param.Bool(False, "Is this interface a mouse, if not a keyboard")
int_delay = '1us'
class Pl111(AmbaDmaDevice):
type = 'Pl111'
+ cxx_header = "dev/arm/pl111.hh"
# Override the default clock
clock = '24MHz'
vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display")
class RealView(Platform):
type = 'RealView'
+ cxx_header = "dev/arm/realview.hh"
system = Param.System(Parent.any, "system")
pci_cfg_base = Param.Addr(0, "Base address of PCI Configuraiton Space")
mem_start_addr = Param.Addr(0, "Start address of main memory")
#ifndef __DEV_ARM_PL011_H__
#define __DEV_ARM_PL011_H__
+#include "base/bitfield.hh"
+#include "base/bitunion.hh"
#include "dev/io_device.hh"
#include "dev/uart.hh"
#include "params/Pl011.hh"
#include "dev/platform.hh"
#include "params/RealView.hh"
+class Gic;
class IdeController;
class System;
#ifndef __DEV_ARM_LOCALTIMER_HH__
#define __DEV_ARM_LOCALTIMER_HH__
+#include "base/bitunion.hh"
#include "dev/io_device.hh"
#include "params/CpuLocalTimer.hh"
#include <vector>
+#include "base/cp_annotate.hh"
#include "base/statistics.hh"
#include "dev/copy_engine_defs.hh"
#include "dev/pcidev.hh"
class MaltaCChip(BasicPioDevice):
type = 'MaltaCChip'
+ cxx_header = "dev/mips/malta_cchip.hh"
malta = Param.Malta(Parent.any, "Malta")
class MaltaIO(BasicPioDevice):
type = 'MaltaIO'
+ cxx_header = "dev/mips/malta_io.hh"
time = Param.Time('01/01/2009',
"System time to use (0 for actual time, default is 1/1/06)")
year_is_bcd = Param.Bool(False,
class MaltaPChip(BasicPioDevice):
type = 'MaltaPChip'
+ cxx_header = "dev/mips/malta_pchip.hh"
malta = Param.Malta(Parent.any, "Malta")
class Malta(Platform):
type = 'Malta'
+ cxx_header = "dev/mips/malta.hh"
system = Param.System(Parent.any, "system")
cchip = MaltaCChip(pio_addr=0x801a0000000)
io = MaltaIO(pio_addr=0x801fc000000)
#define __DEV_MALTA_IO_HH__
#include "dev/mips/malta.hh"
+#include "dev/mips/malta_cchip.hh"
#include "dev/intel_8254_timer.hh"
#include "dev/io_device.hh"
#include "dev/mc146818.hh"
class MmDisk(BasicPioDevice):
type = 'MmDisk'
+ cxx_header = "dev/sparc/mm_disk.hh"
image = Param.DiskImage("Disk Image")
pio_addr = 0x1F40000000
class DumbTOD(BasicPioDevice):
type = 'DumbTOD'
+ cxx_header = "dev/sparc/dtod.hh"
time = Param.Time('01/01/2009', "System time to use ('Now' for real time)")
pio_addr = 0xfff0c1fff8
class Iob(PioDevice):
type = 'Iob'
+ cxx_header = "dev/sparc/iob.hh"
platform = Param.Platform(Parent.any, "Platform this device is part of.")
pio_latency = Param.Latency('1ns', "Programed IO latency")
class T1000(Platform):
type = 'T1000'
+ cxx_header = "dev/sparc/t1000.hh"
system = Param.System(Parent.any, "system")
fake_clk = IsaFake(pio_addr=0x9600000000, pio_size=0x100000000)
class Cmos(BasicPioDevice):
type = 'Cmos'
cxx_class='X86ISA::Cmos'
+ cxx_header = "dev/x86/cmos.hh"
time = Param.Time('01/01/2012',
"System time to use ('Now' for actual time)")
int_pin = Param.X86IntSourcePin(X86IntSourcePin(),
class I8042(BasicPioDevice):
type = 'I8042'
cxx_class = 'X86ISA::I8042'
+ cxx_header = "dev/x86/i8042.hh"
# This isn't actually used for anything here.
pio_addr = 0x0
data_port = Param.Addr('Data port address')
class I82094AA(BasicPioDevice):
type = 'I82094AA'
cxx_class = 'X86ISA::I82094AA'
+ cxx_header = "dev/x86/i82094aa.hh"
apic_id = Param.Int(1, 'APIC id for this IO APIC')
int_master = MasterPort("Port for sending interrupt messages")
int_latency = Param.Latency('1ns', \
class I8237(BasicPioDevice):
type = 'I8237'
cxx_class = 'X86ISA::I8237'
+ cxx_header = "dev/x86/i8237.hh"
class I8254(BasicPioDevice):
type = 'I8254'
cxx_class = 'X86ISA::I8254'
+ cxx_header = "dev/x86/i8254.hh"
int_pin = Param.X86IntSourcePin(X86IntSourcePin(),
'Pin to signal timer interrupts to')
class I8259(BasicPioDevice):
type = 'I8259'
cxx_class='X86ISA::I8259'
+ cxx_header = "dev/x86/i8259.hh"
output = Param.X86IntSourcePin(X86IntSourcePin(),
'The pin this I8259 drives')
mode = Param.X86I8259CascadeMode('How this I8259 is cascaded')
class Pc(Platform):
type = 'Pc'
+ cxx_header = "dev/x86/pc.hh"
system = Param.System(Parent.any, "system")
pciconfig = PciConfigAll()
class PcSpeaker(BasicPioDevice):
type = 'PcSpeaker'
cxx_class = 'X86ISA::Speaker'
+ cxx_header = "dev/x86/speaker.hh"
i8254 = Param.I8254('Timer that drives the speaker')
class SouthBridge(SimObject):
type = 'SouthBridge'
+ cxx_header = "dev/x86/south_bridge.hh"
platform = Param.Platform(Parent.any, "Platform this device is part of")
_pic1 = I8259(pio_addr=x86IOAddress(0x20), mode='I8259Master')
class X86IntSourcePin(SimObject):
type = 'X86IntSourcePin'
cxx_class = 'X86ISA::IntSourcePin'
+ cxx_header = "dev/x86/intdev.hh"
# A generic pin to receive an interrupt signal generated by another device.
class X86IntSinkPin(SimObject):
type = 'X86IntSinkPin'
cxx_class = 'X86ISA::IntSinkPin'
+ cxx_header = "dev/x86/intdev.hh"
device = Param.SimObject("Device this pin belongs to")
number = Param.Int("The pin number on the device")
class X86IntLine(SimObject):
type = 'X86IntLine'
cxx_class = 'X86ISA::IntLine'
+ cxx_header = "dev/x86/intdev.hh"
source = Param.X86IntSourcePin("Pin driving this line")
sink = Param.X86IntSinkPin("Pin driven by this line")
#define __DEV_X86_SPEAKER_HH__
#include "base/bitunion.hh"
+#include "dev/io_device.hh"
#include "params/PcSpeaker.hh"
namespace X86ISA
class AbstractMemory(MemObject):
type = 'AbstractMemory'
abstract = True
+ cxx_header = "mem/abstract_mem.hh"
range = Param.AddrRange(AddrRange('128MB'), "Address range")
null = Param.Bool(False, "Do not store data, always return zero")
zero = Param.Bool(False, "Initialize memory with zeros")
# currently not modified.
class AddrMapper(MemObject):
type = 'AddrMapper'
+ cxx_header = 'mem/addr_mapper.hh'
abstract = True
# one port in each direction
# (original and remapped), only with an offset.
class RangeAddrMapper(AddrMapper):
type = 'RangeAddrMapper'
+ cxx_header = 'mem/addr_mapper.hh'
# These two vectors should be the exact same length and each range
# should be the exact same size. Each range in original_ranges is
class Bridge(MemObject):
type = 'Bridge'
+ cxx_header = "mem/bridge.hh"
slave = SlavePort('Slave port')
master = MasterPort('Master port')
req_size = Param.Int(16, "The number of requests to buffer")
class BaseBus(MemObject):
type = 'BaseBus'
abstract = True
+ cxx_header = "mem/bus.hh"
slave = VectorSlavePort("vector port for connecting masters")
master = VectorMasterPort("vector port for connecting slaves")
header_cycles = Param.Cycles(1, "cycles of overhead per transaction")
class NoncoherentBus(BaseBus):
type = 'NoncoherentBus'
+ cxx_header = "mem/noncoherent_bus.hh"
class CoherentBus(BaseBus):
type = 'CoherentBus'
+ cxx_header = "mem/coherent_bus.hh"
# with periodic dumping and resetting of stats using schedStatEvent
class CommMonitor(MemObject):
type = 'CommMonitor'
+ cxx_header = "mem/comm_monitor.hh"
# one port in each direction
master = MasterPort("Master port")
class MemObject(ClockedObject):
type = 'MemObject'
abstract = True
+ cxx_header = "mem/mem_object.hh"
# itself.
class SimpleDRAM(AbstractMemory):
type = 'SimpleDRAM'
+ cxx_header = "mem/simple_dram.hh"
# single-ported on the system interface side, instantiate with a
# bus in front of the controller for multiple ports
class SimpleMemory(AbstractMemory):
type = 'SimpleMemory'
+ cxx_header = "mem/simple_mem.hh"
port = SlavePort("Slave ports")
latency = Param.Latency('30ns', "Request to response latency")
latency_var = Param.Latency('0ns', "Request to response latency variance")
class BaseCache(MemObject):
type = 'BaseCache'
+ cxx_header = "mem/cache/base.hh"
assoc = Param.Int("associativity")
block_size = Param.Int("block size in bytes")
hit_latency = Param.Cycles("The hit latency for this cache")
class BasePrefetcher(ClockedObject):
type = 'BasePrefetcher'
abstract = True
+ cxx_header = "mem/cache/prefetch/base.hh"
size = Param.Int(100,
"Number of entries in the hardware prefetch queue")
cross_pages = Param.Bool(False,
class GHBPrefetcher(BasePrefetcher):
type = 'GHBPrefetcher'
cxx_class = 'GHBPrefetcher'
+ cxx_header = "mem/cache/prefetch/ghb.hh"
class StridePrefetcher(BasePrefetcher):
type = 'StridePrefetcher'
cxx_class = 'StridePrefetcher'
+ cxx_header = "mem/cache/prefetch/stride.hh"
class TaggedPrefetcher(BasePrefetcher):
type = 'TaggedPrefetcher'
cxx_class = 'TaggedPrefetcher'
+ cxx_header = "mem/cache/prefetch/tagged.hh"
class Repl(SimObject):
type = 'Repl'
abstract = True
+ cxx_header = "mem/cache/tags/iic_repl/repl.hh"
class GenRepl(Repl):
type = 'GenRepl'
+ cxx_header = "mem/cache/tags/iic_repl/gen.hh"
fresh_res = Param.Int("Fresh pool residency time")
num_pools = Param.Int("Number of priority pools")
pool_res = Param.Int("Pool residency time")
class BasicLink(SimObject):
type = 'BasicLink'
+ cxx_header = "mem/ruby/network/BasicLink.hh"
link_id = Param.Int("ID in relation to other links")
latency = Param.Int(1, "latency")
# The following banwidth factor does not translate to the same value for
class BasicExtLink(BasicLink):
type = 'BasicExtLink'
+ cxx_header = "mem/ruby/network/BasicLink.hh"
ext_node = Param.RubyController("External node")
int_node = Param.BasicRouter("ID of internal node")
bandwidth_factor = 16
class BasicIntLink(BasicLink):
type = 'BasicIntLink'
+ cxx_header = "mem/ruby/network/BasicLink.hh"
node_a = Param.BasicRouter("Router on one end")
node_b = Param.BasicRouter("Router on other end")
bandwidth_factor = 16
class BasicRouter(SimObject):
type = 'BasicRouter'
+ cxx_header = "mem/ruby/network/BasicRouter.hh"
router_id = Param.Int("ID in relation to other routers")
class Topology(SimObject):
type = 'Topology'
+ cxx_header = "mem/ruby/network/Topology.hh"
description = Param.String("Not Specified",
"the name of the imported topology module")
ext_links = VectorParam.BasicExtLink("Links to external nodes")
class RubyNetwork(SimObject):
type = 'RubyNetwork'
cxx_class = 'Network'
+ cxx_header = "mem/ruby/network/Network.hh"
abstract = True
number_of_virtual_networks = Param.Int(10, "");
topology = Param.Topology("");
class FaultModel(SimObject):
type = 'FaultModel'
cxx_class = 'FaultModel'
+ cxx_header = "mem/ruby/network/fault_model/FaultModel.hh"
baseline_fault_vector_database = VectorParam.Float([
5, 40, 0.080892, 0.109175, 0.018864, 0.130408, 0.059724, 0.077571, 0.034830, 0.083430, 0.067500, 0.121500,
class BaseGarnetNetwork(RubyNetwork):
type = 'BaseGarnetNetwork'
+ cxx_header = "mem/ruby/network/garnet/BaseGarnetNetwork.hh"
abstract = True
ni_flit_size = Param.Int(16, "network interface flit size in bytes")
vcs_per_vnet = Param.Int(4, "virtual channels per virtual network");
class NetworkLink_d(SimObject):
type = 'NetworkLink_d'
+ cxx_header = "mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh"
link_id = Param.Int(Parent.link_id, "link id")
link_latency = Param.Int(Parent.latency, "link latency")
vcs_per_vnet = Param.Int(Parent.vcs_per_vnet,
class CreditLink_d(NetworkLink_d):
type = 'CreditLink_d'
+ cxx_header = "mem/ruby/network/garnet/fixed-pipeline/CreditLink_d.hh"
# Interior fixed pipeline links between routers
class GarnetIntLink_d(BasicIntLink):
type = 'GarnetIntLink_d'
+ cxx_header = "mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.hh"
# The detailed fixed pipeline bi-directional link include two main
# forward links and two backward flow-control links, one per direction
nls = []
# Exterior fixed pipeline links between a router and a controller
class GarnetExtLink_d(BasicExtLink):
type = 'GarnetExtLink_d'
+ cxx_header = "mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.hh"
# The detailed fixed pipeline bi-directional link include two main
# forward links and two backward flow-control links, one per direction
nls = []
class GarnetNetwork_d(BaseGarnetNetwork):
type = 'GarnetNetwork_d'
+ cxx_header = "mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.hh"
buffers_per_data_vc = Param.Int(4, "buffers per data virtual channel");
buffers_per_ctrl_vc = Param.Int(1, "buffers per ctrl virtual channel");
class GarnetRouter_d(BasicRouter):
type = 'GarnetRouter_d'
cxx_class = 'Router_d'
+ cxx_header = "mem/ruby/network/garnet/fixed-pipeline/Router_d.hh"
vcs_per_vnet = Param.Int(Parent.vcs_per_vnet,
"virtual channels per virtual network")
virt_nets = Param.Int(Parent.number_of_virtual_networks,
class NetworkLink(SimObject):
type = 'NetworkLink'
+ cxx_header = "mem/ruby/network/garnet/flexible-pipeline/NetworkLink.hh"
link_id = Param.Int(Parent.link_id, "link id")
link_latency = Param.Int(Parent.latency, "link latency")
vcs_per_vnet = Param.Int(Parent.vcs_per_vnet,
# Interior fixed pipeline links between routers
class GarnetIntLink(BasicIntLink):
type = 'GarnetIntLink'
+ cxx_header = "mem/ruby/network/garnet/flexible-pipeline/GarnetLink.hh"
# The flexible pipeline bi-directional link only include two main
# forward links and no backward flow-control links
nls = []
# Exterior fixed pipeline links between a router and a controller
class GarnetExtLink(BasicExtLink):
type = 'GarnetExtLink'
+ cxx_header = "mem/ruby/network/garnet/flexible-pipeline/GarnetLink.hh"
# The flexible pipeline bi-directional link only include two main
# forward links and no backward flow-control links
nls = []
class GarnetNetwork(BaseGarnetNetwork):
type = 'GarnetNetwork'
+ cxx_header = "mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.hh"
buffer_size = Param.Int(0,
"default buffer size; 0 indicates infinite buffering");
number_of_pipe_stages = Param.Int(4, "router pipeline stages");
class GarnetRouter(BasicRouter):
type = 'GarnetRouter'
cxx_class = 'Router'
+ cxx_header = "mem/ruby/network/garnet/flexible-pipeline/Router.hh"
vcs_per_vnet = Param.Int(Parent.vcs_per_vnet,
"virtual channels per virtual network")
virt_nets = Param.Int(Parent.number_of_virtual_networks,
class SimpleExtLink(BasicExtLink):
type = 'SimpleExtLink'
+ cxx_header = "mem/ruby/network/simple/SimpleLink.hh"
class SimpleIntLink(BasicIntLink):
type = 'SimpleIntLink'
+ cxx_header = "mem/ruby/network/simple/SimpleLink.hh"
class SimpleNetwork(RubyNetwork):
type = 'SimpleNetwork'
+ cxx_header = "mem/ruby/network/simple/SimpleNetwork.hh"
buffer_size = Param.Int(0,
"default buffer size; 0 indicates infinite buffering");
endpoint_bandwidth = Param.Int(1000, "bandwidth adjustment factor");
class RubyProfiler(SimObject):
type = 'RubyProfiler'
cxx_class = 'Profiler'
+ cxx_header = "mem/ruby/profiler/Profiler.hh"
hot_lines = Param.Bool(False, "")
all_instructions = Param.Bool(False, "")
num_of_sequencers = Param.Int("")
class RubyController(SimObject):
type = 'RubyController'
cxx_class = 'AbstractController'
+ cxx_header = "mem/ruby/slicc_interface/AbstractController.hh"
abstract = True
version = Param.Int("")
cntrl_id = Param.Int("")
class RubyCache(SimObject):
type = 'RubyCache'
cxx_class = 'CacheMemory'
+ cxx_header = "mem/ruby/system/CacheMemory.hh"
size = Param.MemorySize("capacity in bytes");
latency = Param.Int("");
assoc = Param.Int("");
class RubyDirectoryMemory(SimObject):
type = 'RubyDirectoryMemory'
cxx_class = 'DirectoryMemory'
+ cxx_header = "mem/ruby/system/DirectoryMemory.hh"
version = Param.Int(0, "")
size = Param.MemorySize("1GB", "capacity in bytes")
use_map = Param.Bool(False, "enable sparse memory")
abstract = True
type = 'MemoryControl'
cxx_class = 'MemoryControl'
+ cxx_header = "mem/ruby/system/MemoryControl.hh"
version = Param.Int("");
ruby_system = Param.RubySystem("")
class RubyMemoryControl(MemoryControl):
type = 'RubyMemoryControl'
cxx_class = 'RubyMemoryControl'
+ cxx_header = "mem/ruby/system/RubyMemoryControl.hh"
version = Param.Int("");
# Override the default clock
class RubySystem(ClockedObject):
type = 'RubySystem'
+ cxx_header = "mem/ruby/system/System.hh"
random_seed = Param.Int(1234, "random seed used by the simulation");
randomization = Param.Bool(False,
"insert random delays on message enqueue times");
class RubyPort(MemObject):
type = 'RubyPort'
abstract = True
+ cxx_header = "mem/ruby/system/RubyPort.hh"
slave = VectorSlavePort("CPU slave port")
master = VectorMasterPort("CPU master port")
version = Param.Int(0, "")
class RubyPortProxy(RubyPort):
type = 'RubyPortProxy'
+ cxx_header = "mem/ruby/system/RubyPortProxy.hh"
class RubySequencer(RubyPort):
type = 'RubySequencer'
cxx_class = 'Sequencer'
+ cxx_header = "mem/ruby/system/Sequencer.hh"
icache = Param.RubyCache("")
dcache = Param.RubyCache("")
max_outstanding_requests = Param.Int(16,
class DMASequencer(RubyPort):
type = 'DMASequencer'
+ cxx_header = "mem/ruby/system/DMASequencer.hh"
class RubyWireBuffer(SimObject):
type = 'RubyWireBuffer'
cxx_class = 'WireBuffer'
+ cxx_header = "mem/ruby/system/WireBuffer.hh"
class $py_ident(RubyController):
type = '$py_ident'
+ cxx_header = 'mem/protocol/${c_ident}.hh'
''')
code.indent()
for param in self.config_parameters:
# dict to look up SimObjects based on path
instanceDict = {}
+# Did any of the SimObjects lack a header file?
+noCxxHeader = False
+
def public_value(key, value):
return key.startswith('_') or \
isinstance(value, (FunctionType, MethodType, ModuleType,
init_keywords = { 'abstract' : bool,
'cxx_class' : str,
'cxx_type' : str,
+ 'cxx_header' : str,
'type' : str }
# Attributes that can be set any time
keywords = { 'check' : FunctionType }
cls._value_dict['cxx_type'] = '%s *' % cls._value_dict['cxx_class']
+ if 'cxx_header' not in cls._value_dict:
+ global noCxxHeader
+ noCxxHeader = True
+ print >> sys.stderr, \
+ "warning: No header file specified for SimObject: %s" % name
+
# Export methods are automatically inherited via C++, so we
# don't want the method declarations to get inherited on the
# python side (and thus end up getting repeated in the wrapped
code('#include "params/$cls.hh"')
for param in params:
param.cxx_predecls(code)
+ code('#include "${{cls.cxx_header}}"')
cls.export_method_cxx_predecls(code)
code('''\
/**
__metaclass__ = MetaSimObject
type = 'SimObject'
abstract = True
-
- @classmethod
- def export_method_cxx_predecls(cls, code):
- code('''
-#include <Python.h>
-
-#include "sim/serialize.hh"
-#include "sim/sim_object.hh"
-''')
+ cxx_header = "sim/sim_object.hh"
@classmethod
def export_method_swig_predecls(cls, code):
baseInstances = instanceDict.copy()
def clear():
- global allClasses, instanceDict
+ global allClasses, instanceDict, noCxxHeader
allClasses = baseClasses.copy()
instanceDict = baseInstances.copy()
+ noCxxHeader = False
# __all__ defines the list of symbols that get exported when
# 'from config import *' is invoked. Try to keep this reasonably
class BaseTLB(SimObject):
type = 'BaseTLB'
abstract = True
+ cxx_header = "sim/tlb.hh"
class ClockedObject(SimObject):
type = 'ClockedObject'
abstract = True
+ cxx_header = "sim/clocked_object.hh"
# Clock period of this object, with the default value being the
# clock period of the parent object, unproxied at instantiation
type = 'InstTracer'
cxx_class = 'Trace::InstTracer'
abstract = True
+ cxx_header = "sim/insttracer.hh"
class Process(SimObject):
type = 'Process'
abstract = True
+ cxx_header = "sim/process.hh"
input = Param.String('cin', "filename for stdin")
output = Param.String('cout', 'filename for stdout')
errout = Param.String('cerr', 'filename for stderr')
system = Param.System(Parent.any, "system process will run on")
max_stack_size = Param.MemorySize('64MB', 'maximum size of the stack')
- @classmethod
- def export_method_cxx_predecls(cls, code):
- code('#include "sim/process.hh"')
-
@classmethod
def export_methods(cls, code):
code('bool map(Addr vaddr, Addr paddr, int size);')
class LiveProcess(Process):
type = 'LiveProcess'
+ cxx_header = "sim/process.hh"
executable = Param.String('', "executable (overrides cmd[0] if set)")
cmd = VectorParam.String("command line (executable plus arguments)")
env = VectorParam.String([], "environment settings")
return 'root'
type = 'Root'
+ cxx_header = "sim/root.hh"
full_system = Param.Bool("if this is a full system simulation")
class System(MemObject):
type = 'System'
+ cxx_header = "sim/system.hh"
system_port = MasterPort("System port")
# Override the clock from the ClockedObject which looks at the