soc/sdram: add capability to share L2 cache in multi-CPU SoCs

diff --git a/misoclib/soc/sdram.py b/misoclib/soc/sdram.py
index 124b714451dd3f12512d2d51bc6fb362bcd1492b..c21f2f74ee9ad7e63db06ee9e0a9e6a08a4ca43e 100644 (file)
--- a/misoclib/soc/sdram.py
+++ b/misoclib/soc/sdram.py
@@ -26,6 +26,13 @@ class SDRAMSoC(SoC):
         else:
             self.sdram_controller_settings = sdram_controller_settings
         self._sdram_phy_registered = False
+        self._wb_sdram_ifs = []
+        self._wb_sdram = wishbone.Interface()
+
+    def add_wb_sdram_if(self, interface):
+        if self.finalized:
+            raise FinalizeError
+        self._wb_sdram_ifs.append(interface)
 
     def register_sdram_phy(self, phy):
         if self._sdram_phy_registered:
@@ -47,6 +54,11 @@ class SDRAMSoC(SoC):
         main_ram_size = min(main_ram_size, 256*1024*1024)
         l2_size = self.sdram_controller_settings.l2_size
 
+               # add a wishbone interface to the DRAM
+        wb_sdram = wishbone.Interface()
+        self.add_wb_sdram_if(wb_sdram)
+        self.register_mem("main_ram", self.mem_map["main_ram"], wb_sdram, main_ram_size)
+
         # LASMICON frontend
         if isinstance(self.sdram_controller_settings, LASMIconSettings):
             if self.sdram_controller_settings.with_bandwidth:
@@ -57,9 +69,8 @@ class SDRAMSoC(SoC):
                 self.submodules.memtest_r = memtest.MemtestReader(self.sdram.crossbar.get_master())
 
             if l2_size:
-                sdram_bus = wishbone.Interface()
                 lasmim = self.sdram.crossbar.get_master()
-                l2_cache = wishbone.Cache(l2_size//4, sdram_bus, wishbone.Interface(lasmim.dw))
+                l2_cache = wishbone.Cache(l2_size//4, self._wb_sdram, wishbone.Interface(lasmim.dw))
                 # XXX Vivado ->2015.1 workaround, Vivado is not able to map correctly our L2 cache.
                 # Issue is reported to Xilinx and should be fixed in next releases (2015.2?).
                 # Remove this workaround when fixed by Xilinx.
@@ -70,13 +81,11 @@ class SDRAMSoC(SoC):
                 else:
                     self.submodules.l2_cache = l2_cache
                 self.submodules.wishbone2lasmi = wishbone2lasmi.WB2LASMI(self.l2_cache.slave, lasmim)
-                self.register_mem("main_ram", self.mem_map["main_ram"], sdram_bus, main_ram_size)
 
         # MINICON frontend
         elif isinstance(self.sdram_controller_settings, MiniconSettings):
-            sdram_bus = wishbone.Interface()
             if l2_size:
-                l2_cache = wishbone.Cache(l2_size//4, sdram_bus, self.sdram.controller.bus)
+                l2_cache = wishbone.Cache(l2_size//4, self._wb_sdram, self.sdram.controller.bus)
                 # XXX Vivado ->2015.1 workaround, Vivado is not able to map correctly our L2 cache.
                 # Issue is reported to Xilinx and should be fixed in next releases (2015.2?).
                 # Remove this workaround when fixed by Xilinx.
@@ -87,11 +96,14 @@ class SDRAMSoC(SoC):
                 else:
                     self.submodules.l2_cache = l2_cache
             else:
-                self.submodules.converter = wishbone.Converter(sdram_bus, self.sdram.controller.bus)
-            self.register_mem("main_ram", self.mem_map["main_ram"], sdram_bus, main_ram_size)
+                self.submodules.converter = wishbone.Converter(self._wb_sdram, self.sdram.controller.bus)
 
     def do_finalize(self):
         if not self.integrated_main_ram_size:
             if not self._sdram_phy_registered:
                 raise FinalizeError("Need to call SDRAMSoC.register_sdram_phy()")
+
+            # arbitrate wishbone interfaces to the DRAM
+            self.submodules.wb_sdram_con = wishbone.Arbiter(self._wb_sdram_ifs,
+                                                            self._wb_sdram)
         SoC.do_finalize(self)