fix form and pseudo-code for fmvis, tests in 64-bit mode

diff --git a/openpower/isa/av.mdwn b/openpower/isa/av.mdwn
index 6d26841ce18e822bb1212f2f6f17443fc092abe5..7a035168c9964c33cddccb3089c630239a016717 100644 (file)
--- a/openpower/isa/av.mdwn
+++ b/openpower/isa/av.mdwn
@@ -208,13 +208,15 @@ Special Registers Altered:
 
 # Load Floating-Point Immediate
 
-X-Form
+DX-Form
 
 * fmvis FRS,SI
 
 Pseudo-code:
 
-    FRS <- EXTS(SI)
+    bf16 <- d0 || d1 || d2
+    fp32 <- bf16 || [0]*16
+    FRS  <- Single_to_Double(fp32)
 
 Special Registers Altered:
 

diff --git a/src/openpower/test/alu/fmvis_cases.py b/src/openpower/test/alu/fmvis_cases.py
index 26d9692b99b6e90b8ab1fdc1aa79fc5ba9556d21..fc3e56fc5ac5e62e8012d6a506704ba9420ae885 100644 (file)
--- a/src/openpower/test/alu/fmvis_cases.py
+++ b/src/openpower/test/alu/fmvis_cases.py
@@ -19,8 +19,8 @@ class FMVISTestCase(TestAccumulatorBase):
                        ])
         lst = list(lst)
 
-        expected_fprs = [0] * 32
-        expected_fprs[5] = 0x40000000
-        expected_fprs[6] = 0x21220000
-        expected_fprs[7] = 0x3E800000
+        expected_fprs = [0] * 64
+        expected_fprs[5] = 0x4000000000000000
+        expected_fprs[6] = 0x2122000000000000
+        expected_fprs[7] = 0x3E80000000000000
         self.add_case(Program(lst, bigendian), expected_fprs)